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PDF P4N80E Data sheet ( Hoja de datos )
| Número de pieza | P4N80E | |
| Descripción | MTP4N80E | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de P4N80E (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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MOTOROLA
www.DatSaSEheMetI4CU.OcoNm DUCTOR TECHNICAL DATA
Order this document
by MTP4N80E/D
TMOS E-FE™T t4U.™.com MTP4N80EDesigner's
Data Sheet
Motorola Preferred Device
NP–oCwhearntnaFeSilehEldenehEafnfceecmteTnrta–MnsoidsetoSrilicon GateThis high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage–blocking capability without
adegrading performance over time. In addition, this advanced TMOS
.DE–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
wdrain–to–source diode with a fast recovery time. Designed for high
wvoltage, high speed switching applications in power supplies,
w converters and PWM motor controls, these devices are particularly
mwell suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
oagainst unexpected voltage transients.
.c• Robust High Voltage Termination
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
U• Diode is Characterized for Use in Bridge Circuits
t4• IDSS and VDS(on) Specified at Elevated Temperature
TMOS POWER FET
4.0 AMPERES
800 VOLTS
RDS(on) = 3.0 OHM
®
D
eeMAXIMUM RATINGS (TC = 25°C unless otherwise noted)
hRating
G
CASE 221A–06, Style 5
TO–220AB
S
Symbol
Value
Unit
Drain–Source Voltage
SDrain–Gate Voltage (RGS = 1.0 MΩ)
taGate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
VDSS
800 Vdc
VDGR 800 Vdc
VGS
± 20 Vdc
VGSM ± 40 Vpk
aDrain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
.DTotal Power Dissipation
Derate above 25°C
ID 4.0 Adc
ID 2.9
IDM 12 Apk
PD 125 Watts
1.0 W/°C
wOperating and Storage Temperature Range
TJ, Tstg
– 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
w(VDD = 100 Vdc, VGS = 10 Vdc, IL = 8.0 Apk, L = 10 mH, RG = 25 Ω)
EAS
320 mJ
Thermal Resistance — Junction to Case
w mThermal Resistance — Junction to Ambient
RθJC
RθJA
1.0 °C/W
62.5
.coMaximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
Ucurves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
t4E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
ataSheePreferred devices are Motorola recommended choices for future use and best overall value.
w.DREV 5
ww© MMoototororloa,laIncT.M19O96S Power MOSFET Transistor Device Data
1
1 page  
www.DataSheet4U.com
10
8
6 Q1
QT
Q2
VGS
500
400
300
4 200
ID = 4 A
TJ = 25°C
2 100
Q3 VDS
00
0 6 12 18 24 30 36
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
1000
VDD = 400 V
ID = 4 A
VGS = 10 V
TJ = 25°C
MTP4N80E
100
td(off)
tf
tr
td(on)
10
1 10
RG, GATE RESISTANCE (OHMS)
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
4.0
3.6 VGS = 0 V
3.2 TJ = 25°C
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
0.50 0.54 0.58 0.62 0.66 0.70 0.74 0.78 0.82
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 µs. In addition the total power aver-
aged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases non–linearly with an in-
crease of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
Motorola TMOS Power MOSFET Transistor Device Data
5
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