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PDF ICS2509C Data sheet ( Hoja de datos )
| Número de pieza | ICS2509C | |
| Descripción | 3.3V Phase-Lock Loop Clock Driver | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS2509C
3.3V Phase-Lock Loop Clock Driver
General Description
The ICS2509C is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology to
align, in both phase and frequency, the CLKIN signal with
the CLKOUT signal. It is specifically designed for use with
synchronous SDRAMs. The ICS2509C operates at 3.3V VCC
and drives up to nine clock loads.
One bank of five outputs and one bank of four outputs provide
nine low-skew, low-jitter copies of CLKIN. Output signal
duty cycles are adjusted to 50 percent, independent of the
duty cycle at CLKIN. Each bank of outputs can be enabled or
disabled separately via control (OEA and OEB) inputs. When
the OE inputs are high, the outputs align in phase and
frequency with CLKIN; when the OE inputs are low, the
outputs are disabled to the logic low state.
Features
• Meets or exceeds PC133 registered DIMM
specification 1.1
• Spread Spectrum Clock Compatible
• Distributes one clock input to one bank of five and one
bank of four outputs
• Separate output enable(OEA,OEB) for each output bank
• Operating frequency 25 MHz to 175 Mhz
• External feedback input (FBIN) terminal is used to
synchrionize the outputs to the clock input
• No external RC network required
• Operates at 3.3V Vcc
• Plastic 24-pin 173mil TSSOP package
The ICS2509C does not require external RC filter
components. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost. The
buffer mode shuts off the PLL and connects the input directly
to the output buffer. This buffer mode, the ICS2509C can be
use as low skew fanout clock buffer device. The ICS2509C
comes in 24 pin 173mil Thin Shrink Small-Outline package
(TSSOP) package.
Block Diagram
FBIN
CLKIN
AVCC
OEA
PLL
OEB
2509 C Rev C 06/15/01
FBOUT
CLKA0
CLKA1
CLKA2
CLKA3
CLKA4
CLKB0
CLKB1
CLKB2
CLKB3
Pin Configuration
AGND
VCC
CLKA0
CLKA1
CLKA2
GND
GND
CLKA3
CLKA4
VCC
OEA
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
24 CLKIN
23 AVCC
22 VCC
21 CLKB0
20 CLKB1
19 GND
18 GND
17 CLKB2
16 CLKB3
15 VCC
14 OEB
13 FBIN
24 Pin TSSOP
4.40 mm. Body, 0.65 mm. pitch
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
ICS2509C
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
30 pF 500 Ω
Figure 1. Load Circuit for Outputs
Notes:
1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following
Figure 2. VoltageWaveforms
Propagation DelayTimes
characteristics: PRR ≤ 133MHz, ZO = 5 0 Ω, Tr ≤1.2ns, Tf ≤1.2ns.
3. The outputs are measured one at a time with one transition per measurement.
Figure 3. Phase Error and Skew Calculations
5
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| PDF Descargar | [ Datasheet ICS2509C.PDF ] | |
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