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PDF ICS2595 Data sheet ( Hoja de datos )
| Número de pieza | ICS2595 | |
| Descripción | User-Programmable Dual High-Performance Clock Generator | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS2595
Not recommended for new designs
User-Programmable Dual High-Performance Clock Generator
Description
The ICS2595 is a dual-PLL (phase-locked loop) clock
generator specifically designed for high-resolution, high-
refresh rate, video applications. The video PLL generates
any of 16 pre-programmed frequencies through selection
of the address lines FS0-FS3. Similarly, the auxiliary PLL
can generate any one of four pre-programmed frequencies
via the MS0 & MS1 lines.
A unique feature of the ICS2595 is the ability to redefine
frequency selections in both the VCLK and MCLK synthesiz-
ers after power-up. This permits complete set-up of the
frequency table upon system initialization.
Features
• Advanced ICS monolithic phase-locked loop
technology for extremely low jitter
• Supports high-resolution graphics - VCLK
output to 145 MHz
• Completely integrated - requires only external
crystal (or reference frequency and decoupling)
• Power-down modes support portable computing
• Sixteen selectable VCLK frequencies
(all user re-programmable)
• Four selectable MCLK frequencies
(all user re-programmable)
Applications
• PC Graphics
• VGA/Supper VGA/XGA Applications
Block Diagram
Pin Configuration
20-Pin DIP or SOIC
ICS2595 RevB 3/2/00
1 page  
ICS2595
Read/Write* Control Bit
When set to a “0,” the ICS2595 shift register will transfer its
contents to the selected memory register at the completion
of the programming sequence.
When this bit is a “1,” the selected memory location will be
transferred to the shift register to permit a subsequent readback
of data. No modification of device memory will be performed.
"Readback" of a location in the frequency table may be
performed by execution the 64 step readback sequence. The
readback sequence is shown in Table 2. Note that the readback
sequence is essentially the programming sequence (with the
R/W* bit set high) followed by the actual data readback.
The bi-directional FS0 pin will convert to output mode after
the 42nd nibble write and the logic level output will be that
of the first data bit (N0). Subsequent "clocking" by latching
FS3 to "0" and then to "1" will shift out the remaining data
bits. The last two writes will return the FS0 pin to input
mode.
EXTFREQ Input
The EXTFREQ input allows an externally generated fre-
quency to be routed to the VCLK or MCLK output pins
under device programming control. If the EXTFREQ bit is
set (logic “1”) at the selected address location, the frequency
applied to the EXTFREQ input will be routed to the output
instead of the frequency generated by the VCLK (or MCLK)
PLL.
When setting the EXTFREQ bit to a “1,” be sure that the D0
and D1 bits are not both set to “1” also, unless it is intended
that the phase-locked loop be shutdown as well.
Power Conservation
The ICS2595 supports power conservation by permitting
either or both of the phase-locked loops to be disabled. This
can be done by programming a particular address to have
EXTFREQ, D0, & D1 bits set to a logic “1.” Any frequency
applied to the EXTFREQ pin will still be passed through the
output multiplexer and appear at the respective output.The
crystal oscillator is not affected by this power-down function
and will continue to operate normally.
Frequency Synthesizer Description
Refer to the block diagram of the ICS2595. The ICS2595
generates its output frequencies using phase-locked loop
techniques. The phase-locked loop (or PLL) is a closed-loop
feedback system that drives the output frequency to be
ratiometrically related to the reference frequency pro-vided
to the PLL. The phase-frequency detector shown in the
block diagram drives the VCO to a frequency that will cause
the two inputs to the phase-frequency detector to be matched
in frequency and phase. This occurs when:
FVCO = FXTAL1*
N
R
where N is the effective modulus of the feedback divider
chain and R is the modulus of the reference divider chain.
The feedback divider on the ICS2595 may be set to any
integer value from 257 to 512. This is done by the setting of
the N0-N7 bits. The standard reference divider on the ICS2595
is fixed to a value of 43 (this may be set to a different value
via ROM programming; contact factory). The ICS2595 is
equipped with a post-divider and multiplexer that allows
the output frequency range to be scaled down from that of
the VCO by a factor of 2, 4, or 8,
therefore, the VCO frequency range will be from 5.976 to
11.906 (257/43 to 512/43) of the reference frequency. The
output frequency range will be from 0.747 to 11.906 times
the reference frequency. Worst case accuracy for any desired
fre-quency within that range will be 0.2%.
If a 14.31818 MHz reference is used, the output frequency
range would be from 10.697 MHz to 170.486 MHz (but the
upper end is first limited to 145 MHz by the ICS2595 output
driver).
Programming Example
Suppose that we want differential CLK output to be 45.723
MHz. We will assume the reference frequency to be 14.31818
MHz.
The VCO frequency range will be 85.565 MHz to 170.486
MHz (5.976 * 14.31818 to 11.906 * 14.31818). We will
need to set the post-divider to two to get an output of 45.723
MHz.
The VCO will then need to be programmed to two times
45.723 MHz, or 91.446 MHz. To calculate the required feed-
5
5 Page 
Frequency Table
PATTERN
Reference Divider
VCLK ADDR
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
MCLK ADDR
0
1
2
3
ICS2595-02
46
VCLK
100.27
125.90
93.06
36.27
50.76
57.03
External Frequency
45.28
135.99
32.20
110.51
80.21
40.11
45.28
75.51
65.49
MCLK
40.42
45.59
N/A
N/A
ICS2595-04
43
VCLK
50.28
56.60
64.93
71.92
80.08
89.90
62.93
74.92
25.14
28.30
31.46
35.96
40.04
44.95
49.94
64.93
MCLK
40.20
41.54
44.54
49.61
ICS2595
11
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| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ICS2595.PDF ] | |
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