IQX240B Datasheet PDF - I-CUBE
Part Number | IQX240B | |
Description | IQX Series | |
Manufacturers | I-CUBE | |
Logo | ||
There is a preview and IQX240B download ( pdf file ) link at the bottom of this page. Total 65 Pages |
Preview 1 page No Preview Available ! et4U.com IQX Family Data SheetFEATURES
he• SRAM-based, in-system programmable
taS• Switch Matrix
a— Non-Blocking
.D— Identical and predictable delays
— One-to-one, one-to-many and many-to-one connections
ww• RapidConfigure™ parallel interface for fast, incremental
w configuration of Switch Matrix and I/O Port attributes
m— 100% JTAG compliant
• Clocked, Latched and Flow-through Dataflow Modes
o— As low as 7.5 ns pin-to-pin delay in flow-through mode
.cand 133 MHz clock rate in registered mode
• I/O Ports
— Individually programmable as input, output or
Ubidirectional
t4— For each I/O Port, clock, clock enable, input enable and
output enable can be selected independently from a large
epool of common control signals
— 12 mA current drive
e— Separated I/O power pins for easy interfacing between
h5V and 3.3V signals
DESCRIPTION
The IQX family of SRAM-based bit-oriented switching devices is
manufactured using a 0.6µ m CMOS process. These devices
offer clock speeds of up to 133 MHz and pin-to-pin delay as low
as 7.5 ns.
The IQX devices are used in applications requiring dynamic
switching and flexible routing / interconnection of signals. These
applications include communication switches, network systems,
DSP / image processing engines and file/video servers.
At the heart of IQX devices is a non-blocking Switch Matrix. A
line in the Switch Matrix can be connected to one or more other
lines. The Switch Matrix lines are connected to I/O Ports with
programmable functional attributes.
The RapidConfigure parallel interface allows connections in the
Switch Matrix to be changed quickly and incrementally. This
interface can also be used to configure I/O Port attributes
individually and incrementally. In either case, data integrity is
maintained on all unchanged signal paths through the device.
The IQX devices support the industry standard JTAG (IEEE
1149.1) interface for boundary scan testing. The same interface
can also used for serially downloading the configuration bit
stream into the devices.
taSShared with
aI/O Control
Signals
I/O Port
I/O Port
.DI/O Port
I/O Port
www omShared with
.cRapidConfigure
t4UInterface Signals
I/O Port
I/O Port
I/O Port
Dedicated
I/O Control Signals
I/O
Control
Signal
Ports
Switch Matrix
[Crossbar Array]
RapidConfigure
Interface
JTAG Configuration Control
heeTDO TDI TMS TCK TRST*
taSFigure 1. IQX Functional Block Diagram
www.DaJune 2000
Revision 5.0
1
|
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Figures
Figure 1. IQX Functional Block Diagram ..................................................................................................1
Figure 2. Switch Matrix Structure ..............................................................................................................9
Figure 3. Switch Matrix Control...............................................................................................................10
Figure 4. Programmable I/O Port .............................................................................................................10
Figure 5. IQX Output Driver and Pull-Up Current...................................................................................10
Figure 6. I/O Control ................................................................................................................................14
Figure 7. IQX RapidConfigure System Interface .....................................................................................16
Figure 8. Reset Circuit ..............................................................................................................................23
Figure 9. Off-line Bit Stream Generation .................................................................................................25
Figure 10. Embedded Bit Stream Generation ...........................................................................................25
Figure 11. Configuring Multiple IQX Devices.........................................................................................26
Figure 12. Test Circuit and Waveform Definition....................................................................................36
Figure 13. Registered Input and Registered Output Mode Timing (ICLK, OCLK Synchronized)..........36
Figure 14. Registered Input Mode Timing ...............................................................................................36
Figure 15. Registered Output Mode Timing.............................................................................................37
Figure 16. I/O Port Timing (Flow–through Mode)...................................................................................37
Figure 17. Input Enable Timing (Flow–through Mode) ...........................................................................37
Figure 18. Output Enable Timing (Flow–through Mode) ........................................................................38
Figure 19. Latched Input Mode Timing....................................................................................................38
Figure 20. Latched Output Mode Timing .................................................................................................38
Figure 21. Key Timing for Register Input, Clock Enable (CKE).............................................................39
Figure 22. Key Timing for Register Output, Clock Enable (CKE) ..........................................................39
Figure 23. Key Timing for Input Enable ..................................................................................................39
Figure 24. Key Timing for Output Enable................................................................................................40
Figure 25. Key Timing for Latch Input, Enable (CKE)............................................................................40
Figure 26. Key Timing for Latch Output, Enable (CKE) .........................................................................40
Figure 27. Key Counter Timing................................................................................................................41
Figure 28. RapidConfigure Timing ..........................................................................................................41
Figure 29. JTAG Timing ..........................................................................................................................42
Figure 30. IQX320 [PBGA/416L] Package Footprint..............................................................................45
Figure 31. IQX240B [PQFP/304L] Package Pinout ..................................................................................48
Figure 32. IQX160 [PQFP/208L] Package Pinout ...................................................................................51
Figure 33. IQX128B [PQFP/184L] Package Pinout.................................................................................54
Figure 34. IQX320 [PBGA/416L] Package Dimensions..........................................................................55
Figure 35. PQFP Package Dimensions .....................................................................................................56
June 2000
Revision 5.0
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for IQX240B electronic component. |
Information | Total 65 Pages | |
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