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What is DP8473?

This electronic component, produced by the manufacturer "National Semiconductor", performs the same function as "Floppy Disk Controller PLUS-2".


DP8473 Datasheet PDF - National Semiconductor

Part Number DP8473
Description Floppy Disk Controller PLUS-2
Manufacturers National Semiconductor 
Logo National Semiconductor Logo 


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July 1990
DP8473 Floppy Disk Controller PLUS-2TM
General Description
This controller is a full featured floppy disk controller that is
software compatible with the mPD765A but also includes
many additional hardware and software enhancements
These enhancements include additional logic specifically re-
quired for an IBM PC PC-XT PC-AT or PS 2 design
This controller incorporates a precision analog data separa-
tor that includes a self trimming delay line and VCO Up to
three external filters are switched automatically depending
on the data rate selected This provides optimal perform-
ance at the standard PC data rates of 250 300 kb s and
500 kb s It also enables optimum performance at 1 Mb s
(MFM) These features combine to provide the lowest possi-
ble PLL bandwidth with the greatest lock range and hence
the widest window margin
This controller includes write precompensation circuitry A
shift register is used to provide a fixed 125 ns early-late
precompensation for all tracks at 500k 300k 250 kb s (83
ns for 1 MB s) or a precompensation value that scales with
(Continued)
Features
Y Fully mPD765A and IBM-BIOS compatible
Y Integrates all PCXT PCAT and most PS 2
On chip 24 MHz Crystal Oscillator
DMA enable logic
IBM compatible address decode of A0 – A2
12 mA mP bus interface buffers
48 mA floppy drive interface buffers
Data rate and drive control registers
Logic
Y Precision analog data separator
Self-calibrating PLL and delay line
Automatically chooses one of three filters
Intelligent read algorithm
Y Two pin programmable precompensation modes
Y Other enhancements
up to 1 Mb s data rate
Implied seek up to 4000 tracks
IBM or ISO formatting
Y Low power CMOS with power down mode
Connection Diagrams
Plastic Leaded Chip Carrier
Dual-In-Line Package
Top View
Order Number DP8473V
See NS Package Number V52A
TL F 9384 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
PLUS-2TM is a trademark of National Semiconductor Corporation
IBM PCXT PCAT and PS 2 are registered trademarks of International Business Machines Corporation
C1995 National Semiconductor Corporation TL F 9384
Top View
TL F 9384 – 2
Order Number DP8473N
See NS Package Number N48A
RRD-B30M105 Printed in U S A

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DP8473 equivalent
Typical Application
Recommended Plastic Chip Carrier Socket
AMP P N 821551-1 or equivalent
FIGURE 2 DP8473 Typical Application
TL F 9384 – 4
Functional Description
This section describes the basic architectural features of
the DP8473 and many of the enhancements provided Re-
fer to Figure 1
765A COMPATIBLE MICRO-ENGINE
The core of the DP8473 is a mPD765A compatible micro-
coded engine This engine consists of a sequencer pro-
gram ROM and disk misc registers This core is clocked by
either a 4 MHz 4 8 MHz or 8 MHz clock selected in the Data
Rate Register Upon this core is added all the glue logic
used to implement a PC-XT or AT or PS 2 floppy controller
as well as the data separator and write precompensation
logic
The controller consists of a microcoded engine that controls
the entire operation of the chip including coordination of
data transfer with the CPU controlling the drive controls
and actually performing the algorithms associated with
reading and writing data to from the disk This includes the
read algorithm for the data separator
Like the mPD765A this controller takes commands and re-
turns data and status through the Data Register in a byte
serial fashion Handshake for command status I O is pro-
vided via the Main Status Register All of the mPD765A
commands are supported as are many other enhanced
commands
DATA SEPARATOR
The internal data separator consists of an analog PLL and
its associated circuitry The PLL synchronizes the raw data
signal read from the disk drive The synchronized signal is
used to separate the encoded clock and data pulses The
data pulses are de-serialized into bytes and then sent to the
mP by the controller
The main PLL consists of four main components a phase
comparator a filter a voltage controlled oscillator (VCO)
and a programmable divider The phase comparator detects
the difference between the phase of the divider’s output and
the phase of the raw data being read from the disk This
phase difference is converted to a current which either
charges or discharges one of the three external filters The
resulting voltage on the filter changes the frequency of the
VCO and the divider output to reduce the phase difference
between the input data and the divider’s output The PLL is
‘‘locked’’ when the frequency of the divider is exactly the
same as the average frequency of the data read from the
disk A block diagram of the data separator is shown in Fig-
ure 3
5


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Featured Datasheets

Part NumberDescriptionMFRS
DP8470The function is Floppy Disk Support Chip Data Separator & Write Precompensation. National SemiconductorNational Semiconductor
DP8473The function is Floppy Disk Controller PLUS-2. National SemiconductorNational Semiconductor

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