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PDF DP8440 Data sheet ( Hoja de datos )
| Número de pieza | DP8440 | |
| Descripción | (DP8440 / DP8441) microCMOS Programmable 16/64 Mbit Dynamic RAM Controller/Driver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DP8440 (archivo pdf) en la parte inferior de esta página. Total 46 Páginas | ||
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February 1995
DP8440-40 DP8440-25 DP8441-40 DP8441-25
microCMOS Programmable 16 64 Mbit
Dynamic RAM Controller Driver
General Description
The DP8440 41 Dynamic RAM Controllers provide an easy
interface between dynamic RAM arrays and 8- 16- 32- and
64-bit microprocessors The DP8440 41 DRAM Controllers
generate all necessary control and timing signals to suc-
cessfully interface and design dynamic memory systems
With significant enhancements over the DP8420 21 22
predecessors the DP8440 41 are suitable for high perform-
ance memory systems These controllers support page and
burst accesses for fast page static column and nibble
DRAMs Refreshes and accesses are arbitrated on chip
RAS low time during refresh and RAS precharge time are
guaranteed by these controllers Separate precharge coun-
ters for each RAS output avoid delayed back to back ac-
cesses due to precharge when using memory interleaving
Programmable features make the DP8440 41 DRAM Con-
trollers flexible enough to fit many memory systems
Features
Y 40 MHz and 25 MHz operation
Y Page detection
Y Automatic CPU burst accesses
Y Support 1 4 16 64 Mbits DRAMs
Y High capacitance drivers for RAS CAS WE and Q out-
puts
Y Support for fast page static column and nibble mode
DRAMs
Y High precision PLL based delay line
Y Byte enable for word size up to 32 bits on the DP8440
or 64 bits on the DP8441
Y Automatic Internal Refresh
Y Staggered RAS-Only refresh
Y Burst and CAS-before-RAS refresh
Y Error scrubbing during refresh
Y TRI-STATE outputs
Y Easy interface to all major microprocessors
Block Diagram
FIGURE 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11718
TL F 11718 – 1
RRD-B30M75 Printed in U S A
1 page  
1 0 Connection Diagrams (Continued)
Top View
FIGURE 4
Order Number DP8440V-40 (40 MHz Operation)
See NS Package Number V84A
TL F 11718 – 3
5
5 Page 
Programming the DP8440 41
4 3 PROGRAMMING SELECTION
RAS LOW AND PRECHARGE TIME
R1 R0
00
01
10
11
2T
3T
4T
5T
DTACK DURING OPENING ACCESS WILL ASSERT AFTER RAS
R3 R2
00
01
10
11
1T
2T
3T
4T
DTACK DURING BURST ACCESS WILL ASSERT AFTER CAS
R5 R4
00
01
10
11
0T
1T
2T
3T
DTACK DURING PAGE ACCESS WILL ASSERT AFTER CAS
R7 R6
00
01
10
11
0T
1T
2T
3T
PAGE SIZE SELECT
R9 R8
0 0 512
0 1 1024
1 0 2048
1 1 4096
WRAP AROUND SIZE
R11 R10
00
01
10
11
2
4
8
16
11
11 Page | ||
| Páginas | Total 46 Páginas | |
| PDF Descargar | [ Datasheet DP8440.PDF ] | |
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