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PDF CY3125 Data sheet ( Hoja de datos )
| Número de pieza | CY3125 | |
| Descripción | CPLD Development Tool for Unix | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CY3125 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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5
eet4U.comWarp® CPLD Development Tool foCrYU3N12IX5Features
h• VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364)
Shigh-level language compilers with the following
tafeatures:
a— Designs are portable across multiple devices
.Dand/or EDA environments
— Facilitates the use of industry-standard simulation
wand synthesis tools for board and system-level
w design
w — Support for functions and libraries facilitating
mmodular design methodology
• IEEE Standard 1076 and 1164 VHDL synthesis
osupports:
— Enumerated types
.c— Operator overloading
— For... Generate statements
U— Integers
• IEEE Standard 1364 Verilog synthesis supports:
t4— Reduction and conditional operators
— Blocking and non-blocking procedural assignments
e— While loops
e— Integers
• Several design entry methods support high-level and
hlow-level design descriptions:
— Behavioral VHDL and Verilog (IF...THEN...ELSE;
SCASE...)
— Boolean
ta— Structural Verilog and VHDL
— Designs can include multiple entry methods (but
aonly one HDL language) in a single design.
• UltraGen™ Synthesis and Fitting Technology:
.D— Infers “modules” such as adders, comparators, etc.,
from behavioral descriptions and replaces them with
circuits pre-optimized for the target device.
w— User-selectable speed and/or area optimization on a
block-by-block basis
w— Perfect communication between synthesis and fit-
ting
w m— Automatic selection of optimal flip-flop type
.co(D type/T type)
— Automatic pin assignment
t4U• Supports for the following Cypress Programmable
Logic Devices:
e— PSI™ (Programmable Serial Interface™)
he— Delta39K™ CPLDs
S— Quantum38K™ CPLDs
ta— Ultra37000™ CPLDs
a— FLASH370i™ CPLDs
.D— MAX340™ CPLDs
— Industry-standard PLDs (16V8, 20V8, 22V10)
• VHDL and Verilog timing model output for use with
third-party simulators
• Static Timing Report:
— Provides timing information for any path broken
down by the different steps of the path
• Architecture Explorer and Dynamic Timing Analysis for
PSI, Delta39K and Quantum38K devices:
— Graphical representation of exactly how your design
will be implemented on your specific target device
— Zoom from the device level down to the macrocell
level
— Determine the timing for any path and view that path
on a graphical representation of the chip
• Workstation support for Sun Solaris™
• On-line documentation and help
Functional Description
VHDL
Verilog
State Machine
UltraGenTM
Synthesis
and
Fitting
Programming
File
Timing
Simulator
VHDL, Verilog
&Third-Party
Simulation Models
Figure 1. Warp® VHDL Design Flow
Warp® is a state-of-the-art HDL compiler for designing with
Cypress’s Complex Programmable Logic Devices (CPLDs).
Warp utilizes a subset of IEEE 1076/1164 VHDL and IEEE
1364 Verilog as its Hardware Description Languages (HDL) for
design entry. Then, it synthesizes and optimizes the entered
design, and outputs a JEDEC or Intel hex file for the desired
PLD or CPLD (see Figure 1). Furthermore, Warp accepts
VHDL or Verilog produced by the Active-HDL FSM graphical
Finite State Machine editor. For simulation, Warp provides a
timing simulator, as well as VHDL and Verilog timing models
for use with third party simulators.
wwCypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
wDocument #: 38-03046 Rev. *A
Revised January 9, 2002
1 page  
CY3125
BEGIN
giveDrink = 0;
returnDime = 0;
returnNickel = 0;
CASE(drinkStatus)
zero: BEGIN
IF (nickel)
drinkStatus = five;
ELSE IF (dime)
drinkStatus = ten;
ELSE IF (quarter)
drinkStatus = twentyfive;
END
five: BEGIN
IF (nickel)
drinkStatus = ten;
ELSE IF (dime)
drinkStatus = fifteen;
ELSE IF (quarter)
BEGIN
drinkStatus = zero;
giveDrink = 1;
END
END
// Several states are omitted in this
// example. The omitted states are ten
// fifteen, twenty, and twentyfive.
owedime: BEGIN
returnDime = 1;
drinkStatus = zero;
END
default: BEGIN
// This makes sure that the state
// machine resets itself if
// it somehow gets into an undefined state.
drinkStatus = zero;
END
ENDCASE
END
ENDMODULE
Verilog is not a strongly typed language. The simplicity and
readability of the following code is increased by use of the
CASEX. The CASEX command accepts “Don’t Cares” and
chooses the branch depending on the value of the expression.
MODULE sequence (clk, s);
INPUT clk;
INOUT s;
WIRE s;
REG temp;
REG[3:0] count;
ALWAYS@(POSEDGE clk)
CASEX(count)
4’b00XX: BEGIN
temp=1;
count=count+1;
end
4’b01XX: BEGIN
temp=0;
count=count+1;
end
4’b100X: BEGIN
temp=1;
count=count+1;
end
default: BEGIN
temp=0;
count=0;
end
ENDCASE
ASSIGN s=temp;
ENDMODULE
Boolean Equations
A second design-entry method available to Warp Verilog users
is Boolean equations. Figure 4 displays a schematic of a simple
one-bit half adder. The following code describes how this one-bit half
adder can be implemented in Warp with Boolean equations:
x
y
Carry
Sum
Figure 4. One-Bit Half Adder
MODULE half_adder(x, y, sum, carry);
INPUT x, y;
OUTPUT sum, carry;
ASSIGN sum = x^y;
ASSIGN carry = x&y;
ENDMODULE
Structural Verilog
While all of the design methodologies described thus far are
high-level entry methods, structural Verilog provides a method
for designing at a very low level. In structural descriptions, the
designer simply lists the components that make up the design
and specifies how the components are wired together.
Figure 5 displays the schematic of a simple 3-bit shift register and
the following code shows how this design can be described in
Warp using structural Verilog.
MODULE shifter3 (clk, x, q0, q1, q2);
INPUT clk, x;
OUTPUT q0, q1, q2;
WIRE q0, q1, q2;
REG q0_temp, q1_temp, q2_temp;
DFF d1(x,clk,q0_temp);
DFF d2(q0_temp,clk,q1_temp);
DFF d3(q1_temp,clk,q2_temp);
ASSIGN q0 = q0_temp;
ASSIGN q1 = q1_temp;
ASSIGN q2 = q2_temp;
ENDMODULE;
Document #: 38-03046 Rev. *A
Page 5 of 8
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CY3125.PDF ] | |
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