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PDF SSD1818A Data sheet ( Hoja de datos )
| Número de pieza | SSD1818A | |
| Descripción | LCD Segment / Common Driver with Controller | |
| Fabricantes | ETC | |
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SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1818A
Advance Information
104 x 65 STN
LCD Segment / Common Driver with Controller
This document contains information on a new product. Specifications and information herein are subject to change without
notice.
http://www.solomon-systech.com
SSD1818A
Rev 1.2 P 1/47 Mar 2004
Copyright 2004 Solomon Systech Limited
1 page  
1. GENERAL DESCRIPTION
SSD1818A is a single-chip CMOS LCD driver with controllers for dot-matrix graphic liquid crystal
display system. It consists of 169 high-voltage driving outputs for driving maximum 104 Segments, 64
Commons and 1 icon line.
SSD1818A consists of 104 x 65 bits Graphic Display Data RAM (GDDRAM). Data/Commands
are sent from common MCU through 8-bit Parallel or 4-wire Serial Interface. 6800-series, 8080-series
compatible Parallel Interface and Serial Peripheral Interface can be selected by hardware configuration.
SSD1818A embeds DC-DC Converter with booster capacitors, On-Chip Oscillator and Bias
Divider so as to reduce the number of external components. With the advanced design for low power
consumption, stable LCD operating voltage and flexible die layout, SSD1818A is suitable for any portable
battery-driven applications requiring long operation period with compact size.
2. FEATURES
Maximum display size: 104 x 64 + 1 Icon Line
Single Supply Operation, 2.4 V - 3.5V
Minimum -12.0V LCD Driving Output Voltage
Low Current Sleep Mode
On-Chip Voltage Generator or External LCD Driving Power Supply Selectable
2X / 3X / 4X/ 5X On-Chip DC-DC Converter
On-Chip Oscillator
On-Chip Bias Divider
Programmable bias ratio [1/4-1/9]
8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface and Serial Peripheral Interface
On-Chip 104 X 65 Graphic Display Data RAM
Row Re-mapping and Column Re-mapping
Vertical Scrolling
Display Offset Control
64 Level Internal Contrast & External Contrast Control
Programmable LCD Driving Voltage Temperature Coefficients
Programmable MUX ratio [2-64 MUX] (Partial display mode)
Available in Gold Bump Die
3. ORDERING INFORMATION
Table 1 - Ordering Information
Ordering Part
Number
SSD1818AZ
SSD1818ATR1
SEG
104
96
COM
64 + 1
54
Package Form
Gold Bump Die
TAB
Reference
Figure 2 on page 7
Figure 14 on page 44
Remark
-
-
SSD1818A
Rev 1.2 P 5/47 Mar 2004
Solomon Systech
5 Page 
D7-D0
These pins are the 8-bit bi-directional data bus in parallel interface mode. D7 is the MSB while D0 is the
LSB. When serial mode is selected, D7 is the serial data input (SDA) and D6 is the serial clock input (SCK).
VDD
These pins are the Chip’s Power Supply pins. These pins are also act as the reference for the DC-DC
Converter output and the LCD driving voltages.
VSS
These pins are the grounding of the chip. They are also act as the reference for the logic pins.
VSS1
These pins are the inputs for internal DC-DC converter. The voltage of generated, VEE, equals to the
multiple factors times the potential different between these pins, VSS1, and VDD. The multiple factors, 2X,
3X, 4X or 5X are selected by different connections of the external capacitors. All voltage levels are
referenced to VDD.
Note: the potential of Vss1 at this input pin must lower than or equal to VSS.
VEE
This is the most negative voltage supply pin of the chip. It can be supplied externally or generated by the
internal DC-DC converter. The internal DC-DC converter is turned on when the internal voltage booster
option is enabled. Please refer to the Set Power Control Register command for detail description.
When using internal DC-DC converter as voltage generator, voltage at this pin is used for internal
referencing only. It CANNOT be used for driving external circuitry.
C1P, C1N, C2N, C2P C3N and C4N
When internal DC-DC voltage converter is used, external capacitor(s) is/are connected between these
pins. Different connections result in different DC-DC converter multiple factors, for example, 2X, 3X, 4X or
5X. For detailed connections, please refer to the voltage converter section in the functional block
description.
VL2, VL3, VL4 and VL5
These pins are outputs with voltage levels equal to the LCD driving voltage. All these voltage levels are
referenced to VDD. The voltage levels can be supplied externally or generated by the internal bias divider.
The bias divider is turned on when the output op-amp buffers are enabled. Please refer to the Set Power
Control Register command for detail description.
The voltage potential relationship of these pins are given as:
VDD > VL2 > VL3 > VL4 > VL5 > VL6
In addition, assume the bias factor is known as a,
VL2 - VDD = 1/a * (VL6 - VDD)
VL3 - VDD = 2/a * (VL6 - VDD)
VL4 - VDD = (a-2)/a * (VL6 - VDD)
VL5 - VDD = (a-1)/a * (VL6 - VDD)
VL6
This pin outputs the most negative LCD driving voltage level. The VL6 can be supplied externally or
generated by the internal regulator. Please refer to the Set Power Control Register command for detail
description.
SSD1818A
Rev 1.2 P 11/47 Mar 2004
Solomon Systech
11 Page | ||
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| PDF Descargar | [ Datasheet SSD1818A.PDF ] | |
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