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PDF AM79C031 Data sheet ( Hoja de datos )
| Número de pieza | AM79C031 | |
| Descripción | (AM79C02/03/031) Power-On Reset and Power Sequencing | |
| Fabricantes | AMD | |
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Power-On Reset and Power
Sequencing for the
Am79C02/03/031 DSLAC™ Devices
Application Note
The purpose of this application note is to consider the behavior of the Dual Subscriber Line Audio-
Processing Circuit (DSLAC™) device on a linecard during power-up. It is necessary to understand
the behavior of the DSLAC device during power-up to ensure a successful linecard design. This
application note discusses the following topics:
s Power-on reset circuit operation
s Warm start
ms Sequence for the application of signals and power rails
oThe DSLAC Power-On Reset Circuit
.cAll DSLAC devices have an internal circuit for generat-
ing a power-on reset when power is first applied to the
VCC rail.The Am79C02 device also has an external hard-
Uware reset pin, but this is not present on the Am79C03
t4and the Am79C031 devices.
Power-On Reset Circuit Operation
eA simplified circuit diagram for the power-on reset of the
eDSLAC devices is shown in Figure 1.
hVCC
ST3
VCC
VCC
T2
ataT1
.DC1
Reset
Figure 1. Simplified Power-On Reset Circuit
wThe reset signal is designed to be Low at initial power-
wup and become High shortly after VCC reaches its nor-
wmal operating voltage. Assume the VCC rail has been
turn on, thus tending to pull the level at the input to the
inverter Low. However, it is acting against T2, which
tends to pull the inverter input High. C1 will continue to
charge so that T1 becomes a lower impedance, even-
tually overpowering T2 so that the input to the inverter
is finally pulled Low. The output of the inverter then
switches High, turning off transistor T2, which latches
the input of the inverter to the Low level and hence its
output is latched High.
The power-on reset circuit has been designed to oper-
ate correctly when the VCC rail is brought from 0 V to +5
V. Thorough investigation of the behavior of the power-
on reset circuit shows that it behaves reliably, even with
very slow VCC ramps. However, one limitation that has
been found is in situations where the VCC rail does not
reach 0 V before power is reapplied to the linecard. In
these circumstances, the capacitor C1, which is nor-
mally discharged by the transistor T3, does not reach
a low enough voltage to turn off transistor T1 so that it
releases control of the input of the inverter. As a result,
the circuit is not reset so that it is ready to generate
another power-on reset to the DSLAC device on the next
application of the VCC rail.
Extensive characterization work indicates that the
DSLAC device will operate correctly as long as the de-
vice does not have power reapplied when the voltage
at 0 V for some time so that capacitors C1 and C2 are at the VCC pin of the device is in the region 0.05 V to
completely uncharged and then VCC is applied. It can
be seen that initially the gate of the n-channel transistor
0.25 V. If the VCC rail does not drop any lower than 0.25
V, then the internal status of the serial microprocessor
T1 will still have 0 V applied to it (due to the uncharged port registers is retained. In addition, a power-on reset
state of C1) and will therefore be turned off. C2 is also is not required for normal operation of the serial port
uncharged, but since one plate of this capacitor is now once power is reapplied, whereas the power-on reset
mat +5 V, the input to the inverter will also be at +5 V. The
.cooutput of the inverter will therefore be Low.The p-chan-
Unel transistor T2 will be turned on and therefore will
t4tend to pull the input to the inverter High (T2 and the
eeinverter in effect form a latch). As the capacitor C1
hcharges via the resistance, the transistor T1 starts to
will operate correctly as long as the VCC rail voltage drops
below 0.05 V before power is reapplied. As a result, in
systems using the DSLAC device where it cannot be
guaranteed that the VCC rail to the DSLAC device will
drop closer to 0 V than 0.05 V before it is reapplied, there
is a small chance that the power-on reset circuit will not
ataSThis document contains information on a product under development at Advanced Micro Devices. The information
.Dis intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
wwwproduct without notice.
Publication# 19756 Rev: A Amendment/0
Issue Date: April 1996
1 page  
Additional Information
DCLK Frequency
The maximum permissible DCLK frequency depends
on the frequency of the internal clock that runs the DSP
engine of the DSLAC device. This internal clock is de-
rived from an internal PLL, which normally generates a
clock frequency of 8.192 MHz from the MCLK signal.
The maximum DCLK rate is half the rate of the PLL
output. If the internal PLL does not receive a power-on
or hardware reset but the MCLK signal is present, then
the internal PLL may run not at 8.192 MHz but at the
MCLK frequency. In this case, the DCLK frequency must
not run at a rate faster than half the rate of the MCLK
frequency or commands may not be received reliably.
DCLK can be asynchronous to MCLK, and thus the
phase relationship between these two signals is unim-
portant.
Operating Power-On Reset in Current
Am79C03x Designs
Problems relating to the failure of the power-on reset to
operate for the Am79C03x device in some circumstanc-
es have only been found during the development stage.
It is not expected that customers will experience prob-
lems with linecards using the Am79C03x device in the
field if similar problems have not been discovered at an
earlier stage in a laboratory environment.
In many customer systems, every register in the
Am79C03x device will be completely reprogrammed a
number of times at regular intervals once power has
been applied to the system. In systems where this is not
done, it is normal to read the coefficients back from the
DSLAC device and resend them if an error is found. In
these circumstances, any possible problem with the
power-on reset of the device will automatically be
cleared at an early stage once sufficient commands
have been sent to the device by this procedure.
In the field, powering down the telecommunications
equipment using the Am79C03x device is likely to be a
rare event. In the unlikely event that a power-on reset
does not occur correctly, it is most easily cured by pow-
ering down the equipment and trying again. The prob-
lem is only likely to occur in systems where the ramp-
down of the VCC rail is slow and in a small window where
the system is powered down for no more and no less
than a few seconds. Failure should only be expected in
a minority of power-down/power-up sequences, even
when the circumstances under which the problem may
occur are present.
Power Interruption Bit (PIB)
The DSLAC power interruption bit (PIB) can be read by
issuing command 55H. In normal circumstances, it gives
an indication that a power interruption has occurred.
This bit is set by the occurrence of a power-on reset. If
such a reset does not occur when power is applied to
the device (for the reasons described above), the PIB
will not be set even though the device had been pow-
ered-down at some point. This is of little consequence
since the inability to communicate with the DSLAC de-
vice will prevent reading of the PIB until a recovery pro-
cedure has been completed. If the recovery sequence
is successful, it can be inferred that a short power inter-
ruption had occurred.
Warm-Start Issues with DSLAC Devices
Systems using the DSLAC device can be considered
as having distributed processor architectures. With
these systems, it is necessary to ensure that the pro-
cessors involved are correctly synchronized to each oth-
er when communicating data. In the case of the DSLAC
device, this means it is necessary to ensure that the
control processor is sending the data that the DSLAC
device requires at the time that the DSLAC device is
expecting to receive it, or vice versa. Problems can arise
if this issue is not taken into consideration; they can
occur during hot insertion of a linecard, during power-
up (when the chip select lines to the DSLAC device may
be changing state randomly), or when the control pro-
cessor is reset (i.e., warm start). In such cases, the
DSLAC device may be in a different state than is expect-
ed by the control processor, and it will be necessary to
clear the problem before continuing.
Consider the worst case where the DSLAC device re-
cently received a write Z-filter coefficients command,
but immediately after this, the control processor re-
ceived a local reset—perhaps due to a watchdog time-
out. The control processor would then begin its se-
quence for initializing the DSLAC devices in the system,
but the DSLAC device that was about to read Z-filter
data would continue to do so, storing the initialization
commands sent to the device as if they were filter data.
The DSLAC device might continue behaving incorrectly
by, for instance, treating subsequent data bytes sent by
the control processor as if they were commands. The
DSLAC device would only regain synchronism with the
control processor at random, having missed much of
the initialization sequence.
In the case of Am79C02 devices, it is possible to detect
that the device is no longer responding to commands
by performing a write/read cycle and checking the re-
sult. It is then possible to synchronize the Am79C02
device to the control processor by simply asserting the
hardware reset. In the case of the Am79C03x device,
there is no hardware reset and it is necessary to clear
any potential problem by including a software module,
an example of which is shown on the next page.
Power-On Reset and Power Sequencing for the Am79C02/03/031 DSLAC Devices
5
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