PDF ICS341 Data sheet ( Hoja de datos )

Número de pieza	ICS341
Descripción	Field Programmable SS VersaClock Synthesizer
Fabricantes	Integrated Circuit Solution
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No Preview Available ! ICS341 Field Programmable SS VersaClock Synthesizer Description The ICS341 is a low cost, single-output, field programmable clock synthesizer. The ICS341 can generate an output frequency from 250 kHz to 200 MHz and may employ Spread Spectrum techniques to reduce system electro-magnetic interference (EMI). Using ICS’ VersaClock™software to configure the PLL and output, the ICS341 contains a One-Time Programmable (OTP) ROM to allow field programmability. Programming features include 4 selectable configuration registers. The device employs Phase-Locked Loop (PLL) techniques to run from a standard fundamental mode, inexpensive crystal, or clock. It can replace multiple crystals and oscillators, saving board space and cost. The device also has a power-down feature that tri-states the clock outputs and turns off the PLLs when the PDTS pin is taken low. The ICS341 is also available in factory programmed custom versions for high-volume applications. Features • 8-pin SOIC package • Highly accurate frequency generation • M/N Multiplier PLL: M = 1...2048, N = 1...1024 • Output clock frequencies up to 200 MHz • Four ROM locations for frequency and spread selection • Spread spectrum capability for lower system EMI • Center or Down Spread up to 4% total • Selectable 32 kHz or 120 kHz modulation • Input crystal frequency from 5 to 27 MHz • Input clock frequency from 2 to 50 MHz • Operating voltage of 3.3 V • Advanced, low-power CMOS process • For two output clocks, use the ICS342. For three output clocks, see the ICS343. For more than three outputs, see the ICS345 or ICS348. • Available in Pb (lead) free packaging Block Diagram 2 S1:0 Crystal or clock input X1/ICLK X2 OTP ROM with PLL Divider Values Crystal Oscillator External capacitors are required with a crystal input. VDD PLL Clock Synthesis, Spred Spectrum and Control Circuitry CLK GND PDTS (output and PLL) MDS 341 E 1 Revision 090704 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com 1 page ICS341 Field Programmable SS VersaClock Synthesizer Parameter Symbol Conditions Input Low Voltage Output High Voltage (CMOS High) VIL VOH ICLK IOH = -4 mA Output High Voltage Output Low Voltage Short Circuit Current Nominal Output Impedance VOH VOL IOS ZO IOH = -12 mA IOL = 12 mA Internal pull-up resistor Internal pull-up resistor Internal pull-down resistor Input Capacitance RPUP RPUP RPD CIN S1:S0 PDTS CLK output inputs Min. VDD-0.4 Typ. Max. VDD/2-1 Units V V 2.4 V 0.4 V ±70 mA 20 Ω 250 kΩ 250 kΩ 525 kΩ 4 pF Note 1: Example with 25 MHz crystal input with output of 33.3 MHz, no load, and VDD = 3.3 V. AC Electrical Characteristics Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C Parameter Symbol Conditions Min. Input Frequency FIN Fundamental Crystal Input Clock 5 2 Output Frequency 0.25 Output Rise Time Output Fall Time Duty Cycle tOR 20% to 80%, Note 1 tOF 80% to 20%, Note 1 Note 2 40 Power-up time PLL lock time from power-up PDTS goes high until stable CLK output, Spread Spectrum Off PDTS goes high until stable CLK output, Spread Spectrum On One Sigma Clock Period Jitter Configuration Dependent Maximum Absolute Jitter tja Deviation from Mean. Configuration Dependent Typ. Max. Units 27 MHz 50 MHz 200 MHz 1 ns 1 ns 49-51 60 % 4 10 ms .2 2 ms 4 7 ms 50 +200 ps ps Note 1: Measured with 15 pF load. Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%. Note 3: ICS test mode output occurs for first 170 clock cycles on CLK for each PLL powered up. PDTS transition high on select address change. MDS 341 E 5 Revision 090704 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com 5 Page

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Número de pieza	Descripción	Fabricantes
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