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PDF MC14538B Data sheet ( Hoja de datos )
| Número de pieza | MC14538B | |
| Descripción | Dual Precision Retiggerable/Resettable Monostable Multivibrator | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC14538B
Dual Precision
Retriggerable/Resettable
Monostable Multivibrator
The MC14538B is a dual, retriggerable, resettable monostable
multivibrator. It may be triggered from either edge of an input pulse,
and produces an accurate output pulse over a wide range of widths, the
duration and accuracy of which are determined by the external timing
components, CX and RX. Output Pulse Width T = RX @ CX (secs)
RX = W
CX = Farads
Features
• Unlimited Rise and Fall Time Allowed on the A Trigger Input
• Pulse Width Range = 10 ms to 10 s
• Latched Trigger Inputs
• Separate Latched Reset Inputs
• 3.0 Vdc to 18 Vdc Operational Limits
• Triggerable from Positive (A Input) or Negative−Going Edge (B−Input)
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Pin−for−pin Compatible with MC14528B and CD4528B (CD4098)
• Use the MC54/74HC4538A for Pulse Widths Less Than 10 ms with
Supplies Up to 6 V
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
−0.5 to VDD + 0.5
V
V
Iin, Iout Input or Output Current
(DC or Transient) per Pin
±10 mA
PD Power Dissipation, per Package
(Note 1)
500 mW
TA Operating Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8−Second Soldering)
−55 to +125
−65 to +150
260
°C
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
SOIC−16
D SUFFIX
CASE 751B
SOIC−16WB
DW SUFFIX
CASE 751G
TSSOP−16
DT SUFFIX
CASE 948F
SOEIAJ−16
F SUFFIX
CASE 966
MARKING DIAGRAMS
16
14538BG
AWLYWW
1
SOIC−16
16
14538BG
AWLYYWW
1
SOIC−16WB
16
14
538B
ALYWG
G
1
TSSOP−16
16
MC14538B
ALYWG
1
SOEIAJ−16
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 11
1
Publication Order Number:
MC14538B/D
1 page  
MC14538B
VDD
RX
2 (14)
CX 1 (15)
4 (12)
A
5 (11)
B
3 (13)
RESET
VDD
P1
Vref1
N1
VSS
+
-C1 ENABLE
+ ENABLE
C2
Vref2 -
CONTROL
QR QR
S RESET LATCH R
RQ
OUTPUT
LATCH
SQ
6 (10)
7 (9)
NOTE: Pins 1, 8 and 15 must
be externally grounded
Figure 1. Logic Diagram
(1/2 of DevIce Shown)
VDD
500 pF
ID
0.1 mF
CERAMIC
RX
VSS CX
RX′
CX′
VSS
Vin A CX/RX
B
RESET
A′
B′
RESET′
Q
CL
Q
Q′ CL
CL
Q′
CL
VSS
20 ns
Vin
90%
10%
20 ns
VDD
0V
Figure 2. Power Dissipation Test Circuit and Waveforms
VSS
PULSE
GENERATOR
PULSE
GENERATOR
PULSE
GENERATOR
VDD
RX
CX
RX′
CX′
A CX/RX
*CL = 50 pF
VSS
B
RESET
A′
B′
RESET′
Q
CL
Q
Q′ CL
CL
Q′
CL
VSS
INPUT CONNECTIONS
Characteristics
Reset
A
tPLH, tPHL, tTLH, tTHL,
T, tWH, tWL
tPLH, tPHL, tTLH, tTHL,
T, tWH, tWL
VDD
VDD
PG1
VSS
tPLH(R), tPHL(R),
tWH, tWL
PG3 PG1
*Includes capacitance of probes,
wiring, and fixture parasitic.
NOTE: Switching test waveforms
for PG1, PG2, PG3 are shown
In Figure 4.
PG1 =
PG2 =
PG3 =
Figure 3. Switching Test Circuit
B
VDD
PG2
PG2
http://onsemi.com
5
5 Page 
MC14538B
PACKAGE DIMENSIONS
SOIC−16 WB
DW SUFFIX
CASE 751G−03
ISSUE D
D
16
A
9
18
16X B
0.25 M T A S B S
B
14X
e
C
T
SEATING
PLANE
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
MILLIMETERS
DIM MIN MAX
A 2.35 2.65
A1 0.10 0.25
B 0.35 0.49
C 0.23 0.32
D 10.15 10.45
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L 0.50 0.90
q 0_ 7_
SOLDERING FOOTPRINT
16X 0.58
1
16X
1.62
11.00
1.27
PITCH
DIMENSIONS: MILLIMETERS
http://onsemi.com
11
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| PDF Descargar | [ Datasheet MC14538B.PDF ] | |
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