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PDF ICS1523 Data sheet ( Hoja de datos )
| Número de pieza | ICS1523 | |
| Descripción | High-Performance Programmable Line-Locked Clock Generator | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS1523
High-Performance Programmable Line-Locked Clock Generator
General Description
The ICS1523 is a low-cost but very high-performance
frequency generator for line-locked and genlocked high-
resolution video applications. Using ICSs advanced
low-voltage CMOS mixed-mode technology, the ICS1523
is an effective clock solution for video projectors and dis-
plays at resolutions from VGA to beyond UXGA.
The ICS1523 offers pixel clock outputs in both differential
(to 250 MHz) and single-ended (to 150 MHz) formats.
Dynamic Phase Adjust circuitry allows user control of
the pixel clock phase relative to the recovered sync signal.
A second differential output at half the pixel clock rate
enables deMUXing of multiplexed analog-to-digital con-
verters. The FUNC pin provides either the regenerated
input from the phase-locked loop (PLL) divider chain out-
put or a re-synchronized and sharpened input HSYNC.
The advanced PLL uses either its internal programmable
feedback divider or an external divider. The device is pro-
grammed by a standard I2C-bus serial interface and is
available in a 24-pin wide small-outline integrated circuit
(SOIC) package.
Features
Pixel clock frequencies up to 250 MHz
Very low jitter
Dynamic Phase Adjust (DPA) for clock outputs
Balanced PECL differential outputs
Single-ended SSTL_3 clock outputs
Double-buffered PLL/DPA control registers
Independent software reset for PLL/DPA
External or internal loop filter selection
Uses 3.3Vdc. Inputs are 5V-tolerant.
I2C-bus serial interface can run at either low speed
(100 kHz) or high speed (400 kHz).
Lock detection
24-pin 300-mil SOIC package
Applications
LCD monitors and video projectors
Genlocking multiple video subsystems
Frequency synthesis
Block Diagram
Pin Configuration
I2C-bus is a trademark of Philips Corporation.
Dynamic Phase Adjust is a trademark of Integrated Circuit Systems, Inc.
ICS1523 Rev S 5/21/99
24-Pin SOIC
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
Block Diagram
ICS1523
5
5 Page 
ICS1523
Name: DPA Control Register
Register: 5h
Index: Read / Write*
Bit Name Bit #
DPA_Res 0-1 0 - 1
Metal_Rev
2-7
Reset Value
3
0
Description
Dynamic Phase Adjust Resolution Select.
Metal Mask Revision Number.
Bit Name
Description
0-1 DPA_Res 0 -1 Dynamic Phase Adjust (DPA) Resolution Select.
It is not recommended to use the DPA above 160 MHz.
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Delay Elements
16
32
Reserved
64 12
CLK Range, MHz
48
24 80
160
40
2-7 Metal_Rev
Metal Mask Revision Number.
After power-up, register bits 7:2 must be written with 111111. After this write,
a read indicates the metal mask revision, as below.
Revision
A
B
C1
C2
D
E
F
G
Bit 7
1
0
1
0
1
1
1
1
Bit 6
1
1
0
0
1
1
1
1
Bit 5
1
1
1
1
0
1
1
1
Bit 4
1
1
1
1
1
0
1
1
Bit 3
1
1
1
1
1
1
0
1
Bit 2
1
1
1
1
1
1
1
0
* Double-buffered register. Actual working registers are loaded during software DPA reset.
See register 8h for details.
11
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet ICS1523.PDF ] | |
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