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PDF 141540 Data sheet ( Hoja de datos )
| Número de pieza | 141540 | |
| Descripción | MC141540 | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Monitor On-Screen Display
CMOS
The MC141540 is a high performance HCMOS device designed to interface
with a microcontroller unit to allow colored symbols or characters to be
displayed on a color monitor. The on–chip PLL allows both multi–system
operation and self–generation of system timing. It also minimizes the MCU’s
burden through its built–in 273 bytes display/control RAM. By storing a full
screen of data and control information, this device has a capability to carry out
‘screen–refresh’ without MCU supervision.
www.DataSheet4U.Scoinmce there is no spacing between characters, special graphics–oriented
characters can be generated by combining two or more character blocks.
Special functions such as character bordering or shadowing, multi–level
windows, double height and double width, and programmable vertical length of
character can also be incorporated. Furthermore, neither massive information
update nor extremely high data transmission rate are expected for normal on–
screen display operation, and serial protocols are implemented in lieu of any
parallel formats to achieve minimum pin count.
• Fixed Resolution: 320 (CGA) Dots per Line
• Fully Programmable Character Array of 10 Rows by 24 Columns
• 273 Bytes Direct Mapping Display RAM Architecture
• Internal PLL Generates a Wide–Ranged System Clock
• For High–End Monitor Application, Maximum Horizontal Frequency is
100 kHz (32 MHz Dot Clock)
• Programmable Vertical Height of Character to Meet Multi–Sync
Requirement
• Programmable Vertical and Horizontal Positioning for Display Center
• 128 Characters and Graphic Symbols ROM
• 10 x 16 Dot Matrix Character
• Character–by–Character Color Selection
• A Maximum of Four Selectable Colors per Row
• Double Character Height and Double Character Width
• Character Bordering or Shadowing
• Three Fully Programmable Background Windows with Overlapping
Capability
• Single Positive 5 V Supply
• MC141540P4 is a Replacement for XC141540P with Two Symbols Added
in ROM Addresses ‘5C’ and ‘5E’
Order this document
by MC141540/D
MC141540
P SUFFIX
PLASTIC DIP
CASE 648
ORDERING INFORMATION
MC141540P4 Plastic DIP
PIN ASSIGNMENT
VSS(A) 1
VCO 2
RP 3
VDD(A) 4
HFLB 5
SS 6
SDA(MOSI) 7
SCL(SCK) 8
16 VSS
15 R
14 G
13 B
12 FBKG
11 HTONE
10 VFLB
9 VDD
REV 1
2/97 TN97031200
M©OMTotOoroRlaO, InLcA. 1997
MC141540
1
1 page  
SS
MOSI
MSB
ÉÉSCKÉÉ
first byte
LSB
ÉÉÉÉlast byte
Figure 2. SPI Protocol
DATA TRANSMISSION FORMATS
After the proper identification by the receiving device, a
data train of arbitrary length is transmitted from the master.
There are three transmission formats from (a) to (c) as stated
below. The data train in each sequence consists of row ad-
www.DataSheet4dUre.csosm(R), column address (C), and display information (I), as
shown in Figure 3. In format (a), display information data
must be preceded with the corresponding row address and
column address. This format is particularly suitable for updat-
ing small amounts of data between different rows. However,
if the current information byte has the same row address as
the one before, format (b) is recommended.
ÎÎroÎÎwadÎÎdr ÎÎÎÎcoÎÎladdÎÎr ÎÎÎÎinfoÎÎÎÎÎÎ
Figure 3. Data Packet
For a full–screen pattern change that requires a massive
information update, or during power–up, most of the row and
column addresses of either (a) or (b) formats will be consec-
utive. Therefore, a more efficient data transmission format (c)
should be applied. This sends the RAM starting row and col-
umn addresses once only, and then treats all subsequent
data as display information. The row and column addresses
will be automatically incremented internally for each display
information data from the starting location. Because Col-
umns 24 through 29 are unused, it is recommended that
these locations are filled with dummy data while using format
(c) to transmit.
The data transmission formats are:
(a) R – > C – > I – > R – > C – > I – > . . . . . . . . .
(b) R – > C – > I – > C – > I – > C – > I. . . . . . .
(c) R – > C – > I – > I – > I – > . . . . . . . . . . . . .
To differentiate the row and column addresses when trans-
ferring data from master, the MSB (most significant bit) is set,
as in Figure 4: ‘1’ to represent row, and ‘0’ for column ad-
dress. Furthermore, to distinguish the column address be-
tween formats (a), (b), and (c), the sixth bit of the column
address is set to ‘1’ which represents format (c), and ‘0’ for
format (a) or (b). However, there is some limitation on using
mixed formats during a single transmission. It is permissible
to change the format from (a) to (b), or from (a) to (c), or from
(b) to (a), but not from (c) back to (a) or (b).
ADDRESS
BIT
FORMAT
7 654321 0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎROW
1 X X X D D D D a, b, c
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎCOLUMN 0 0 X D D D D D a,b
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎCOLUMN 0 1 X D D D D D c
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎX: don’t care
D: valid data
Figure 4. Row & Column Address Bit Patterns
MEMORY MANAGEMENT
Internal RAM is addressed with row and column (coln)
numbers in sequence. The spaces between Row 0 and Coln
0 to Row 9 and Coln 23 are called display registers, and each
contains a character ROM address corresponding to a dis-
play location on the monitor screen. Every data row is
associated with two control registers, which are located at
Coln 30 and 31 of their respective rows, to control the char-
acter display format of that row. In addition, three window
control registers for each of the three windows, together with
three frame control registers, occupy the first 13 columns of
Row 10.
The user should handle the internal RAM address location
with care, especially those rows with double length alphanu-
meric symbols. For example, if Row n is destined to be
double height on the memory map, the data displayed on
screen Rows n and n+1 will be represented by the data con-
tained in the memory address of Row n only. The data of the
next Row n+1 on the memory map will appear on the screen
as n+2 and n+3 row space, and so on. Hence, it is not neces-
sary to load a row of blank data to compensate for the double
row. The user should minimize excessive rows of data in
memory in order to avoid overrunning the limited amount of
row space on the screen.
For rows with double width alphanumeric symbols, only
the data contained in the even numbered columns of the
memory map are shown. Odd numbered columns are
treated in the same manner as double height rows.
0
9
ÎÎÎÎÎÎÎÎÎ00 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ2 ÎÎÎÎÎÎÎÎÎ3 DÎÎÎÎÎÎÎÎÎISPLAÎÎÎÎÎÎÎÎÎ5CYO6RLEÎÎÎÎÎÎÎÎÎUGMISNTÎÎÎÎÎÎÎÎÎER8SÎÎÎÎÎÎÎÎÎ9 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ23 2ÎÎÎÎÎÎÎÎÎ4...12ÎÎÎÎÎÎÎÎÎ29 30ÎÎÎÎÎÎÎÎÎ31ÎÎÎÎÎÎÎÎÎ
10 WINDOW 1 WINDOW 2 WINDOW 3 FRAME CRTL REG
WINDOW AND FRAME CONTROL REGISTERS
Figure 5. Memory Map
MOTOROLA
MC141540
5
5 Page 
DESIGN CONSIDERATIONS
Distortion
Motorola’s MC141540 has a built–in PLL for multi–system
application. Pin 2 voltage is dc–based for the internal VCO in
the PLL. When the input frequency (HFLB) to Pin 5 in-
creases, the VCO frequency will increase accordingly. This
forces the PLL to a higher locked frequency output. The fre-
quency should be equal to 320 x HFLB. This is the pixel dot
clock.
Display distortion is caused by noise on Pin 2. Positive
noise increases the VCO frequency above normal. The cor-
responding scan line will be shorter accordingly. In contrast,
negative noise causes the scan line to be longer. The net re-
sult will be distortion on the display, especially on the right
hand side of the display window.
www.DataSheet4U.Icnomorder to have distortion–free display, the following rec-
ommendations should be considered:
• Only analog part grounds (Pin 2 to Pin 4) can be con-
nected to Pin 1(VSS(A)). VSS and other grounds should be
connected to PCB common ground. The VSS(A) and VSS
grounds should be totally separated (i.e. VSS(A) is float-
ing). Refer to the Application Diagram for the ground con-
nections.
• The dc supply path for Pin 9 (VDD) should be separated
from other switching devices.
• The LC filter should be connected between Pin 9 and Pin
4. Refer to the values used in the Application Diagram.
• Biasing and filter networks should be connected to Pin 2
and Pin 3. Refer to the recommended networks in the Ap-
plication Diagram.
• Two small capacitors can be connected between Pins 2
and 3, and between Pins 3 and 4.
Jittering
Most display jittering is caused by HFLB jittering on Pin 5.
Care must be taken if the HFLB signal comes from the fly-
back transformer. A short path and shielded cable are rec-
ommended for a clean signal. A small capacitor can be
added between Pin 5 and Pin 16 to smooth the signal. Refer
to the value used in the Application Diagram.
Display Dancing
Most display dancing is caused by interference of the seri-
al bus. It can be avoided by adding series resistors to the se-
rial bus.
APPLICATION DIAGRAM
ANALOG GROUND – FLOATING
100 µH
VCC
HFLB
0.1 µF
0.01 µF
1k 2k
3.3 k
0.047
µF
33 pF
330 k 33 pF
330 pF
IIC(SPI) BUS
100
100
100
100 µF
1 VSS(A)
2 VCO
VDD 9
VSS 16
10
µF
0.1 VCC
µF
240
3 RP
R 15 1 k
4 VDD(A)
14 1 k
G
5 HFLB
B 13
6
SS
MOSD
FBKG 12
1k
240
240
MPS2369
FBKG
7
SDA(MOSI)
HTONE 11
HTONE
8
SCL(SCK)
VFLB 10
VFLB
100 R
100 G
100 B
ANALOG GROUND
DIGITAL GROUND
DIGITAL GROUND – COMMON GROUND
MOTOROLA
MC141540
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet 141540.PDF ] | |
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