DP8572A Datasheet PDF - National Semiconductor
| Part Number | DP8572A | |
| Description | Real Time Clock (RTC) | |
| Manufacturers | National Semiconductor | |
| Logo |  |
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May 1993
DP8572A DP8572AM Real Time Clock (RTC)
General Description
The DP8572A (8572AM militarized version) is intended for
use in microprocessor based systems where information is
required for multi-tasking data logging or general time of
day date information This device is implemented in low
voltage silicon gate microCMOS technology to provide low
standby power in battery back-up environments The cir-
cuit’s architecture is such that it looks like a contiguous
block of memory or I O ports The address space is orga-
nized as 2 software selectable pages of 32 bytes This in-
cludes the Control Registers the Clock Counters the Alarm
Compare RAM and the Time Save RAM Any of the RAM
locations that are not being used for their intended purpose
may be used as general purpose CMOS RAM
Time and date are maintained from 1 100 of a second to
year and leap year in a BCD format 12 or 24 hour modes
Day of week day of month and day of year counters are
provided Time is controlled by an on-chip crystal oscillator
requiring only the addition of the crystal and two capacitors
The choice of crystal frequency is program selectable
Power failure logic and control functions have been integrat-
ed on chip This logic is used by the RTC to issue a power
fail interrupt and lock out the mp interface The time power
fails may be logged into RAM automatically when VBB l
VCC Additionally two supply pins are provided When
VBB l VCC internal circuitry will automatically switch from
the main supply to the battery supply Status bits are provid-
ed to indicate initial application of battery power system
power and low battery detect
(Continued)
Features
Y Full function real time clock calendar
12 24 hour mode timekeeping
Day of week and day of years counters
Four selectable oscillator frequencies
Parallel resonant oscillator
Y Power fail features
Internal power supply switch to external battery
Power Supply Bus glitch protection
Automatic log of time into RAM at power failure
Y On-chip interrupt structure
Periodic alarm and power fail interrupts
Y Up to 44 bytes of CMOS RAM
Y MIL-STD-883C compliant
Y SMD 5962-91641-01MJX (future)
Block Diagram
FIGURE 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9980
TL F 9980 – 1
RRD-B30M75 Printed in U S A
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8572AM Military Version
AC Electrical Characteristics
VCC e 4 5V and 5 5V VBB e 3V VPFAIL l VIH CL e 100 pF (unless otherwise specified)
Symbol
Parameter
Min Max Units
READ TIMING
tAR
tRW
tCD
tRD
tDZ
tRCH
tDS
WRITE TIMING
Address Valid Prior to Read Strobe
Read Strobe Width (Note 8)
Chip Select to Data Valid Time
Read Strobe to Valid Data
Read or Chip Select to TRI-STATE
Chip Select Hold after Read Strobe
Minimum Inactive Time between Read or Write Accesses
20
80
0
50
80
70
60
ns
ns
ns
ns
ns
ns
ns
tAW Address Valid before Write Strobe
20 ns
tCW Chip Select to End of Write Strobe
90 ns
tWW Write Strobe Width (Note 9)
80 ns
tDW Data Valid to End of Write Strobe
50 ns
tWCH
Chip Select Hold after Write Strobe
0 ns
Note 8 Read Strobe width as used in the read timing table is defined as the period when both chip select and read inputs are low Hence read commences when
both signals are low and terminates when either signal returns high
Note 9 Write Strobe width as used in the write timing table is defined as the period when both chip select and write inputs are low Hence write commences when
both signals are low and terminates when either signal returns high
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Reference Levels
TRI-STATE Reference
Levels (Note 11)
GND to 3 0V
6 ns (10%–90%)
1 3V
Active High a0 5V
Active Low b0 5V
Note 10 CL e 100 pF includes jig and scope capacitance
Note 11 S1 e VCC for active low to high impedance measurements
S1 e GND for active high to high impedance measurements
S1 e open for all other timing measurements
Capacitance (TA e 25 C f e 1 MHz)
Symbol
Parameter
(Note 12)
Typ Units
CIN Input Capacitance 5 pF
COUT
Output Capacitance
7
pF
Note 12 This parameter is not 100% tested
Note 13 Output rise and fall times 25 ns max (10%–90%) with 100 pF load
TL F 9980 – 24
5
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| Information | Total 22 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ DP8572A.PDF Datasheet ] | |
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