EP1C12Txxxx Datasheet PDF - Altera
Part Number | EP1C12Txxxx | |
Description | Cyclone FPGA Family | |
Manufacturers | Altera | |
Logo | ||
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®
Cyclone
FPGA Family
Data Sheet
Introduction
Preliminary
Information
Features...
The CycloneTM field programmable gate array family is based on a 1.5-V,
0.13-µm, all-layer copper SRAM process, with densities up to 20,060 logic
elements (LEs) and up to 288 Kbits of RAM. With features like phase-
locked loops (PLLs) for clocking and a dedicated double data rate (DDR)
interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory
requirements, Cyclone devices are a cost-effective solution for data-path
applications. Cyclone devices support various I/O standards, including
LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz,
32-bit peripheral component interconnect (PCI), for interfacing with and
supporting ASSP and ASIC devices. Altera also offers new low-cost serial
configuration devices to configure Cyclone devices.
■ 2,910 to 20,060 LEs, see Table 1
■ Up to 294,912 RAM bits (36,864 bytes)
■ Supports configuration through low-cost serial configuration device
■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
■ Support for 66-MHz, 32-bit PCI standard
■ Low speed (311 Mbps) LVDS I/O support
■ Up to two PLLs per device provide clock multiplication and phase
shifting
■ Up to eight global clock lines with six clock resources available per
logic array block (LAB) row
■ Support for external memory, including DDR SDRAM (133 MHz),
FCRAM, and single data rate (SDR) SDRAM
■ Support for multiple intellectual property (IP) cores, including
Altera MegaCore functions and Altera Megafunctions Partners
Program (AMPPSM) megafunctions
Table 1. Cyclone Device Features
Feature
EP1C3
LEs
M4K RAM blocks (128 × 36 bits)
Total RAM bits
PLLs
Maximum user I/O pins (1)
2,910
13
59,904
1
104
Note to Table 1:
(1) This parameter includes global clock pins.
EP1C4
4,000
17
78,336
2
301
EP1C6
5,980
20
92,160
2
185
EP1C12
12,060
52
239,616
2
249
EP1C20
20,060
64
294,912
2
301
Altera Corporation
DS-CYCLONE-1.1
1
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Preliminary Information
Figure 1. Cyclone EP1C12 Device Block Diagram
IOEs
Cyclone FPGA Family Data Sheet
Logic Array
PLL
EP1C12 Device
M4K Blocks
The number of M4K RAM blocks, PLLs, rows, and columns vary per
device. Table 4 lists the resources available in each Cyclone device.
Table 4. Cyclone Device Resources
Device
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
M4K RAM
Columns
Blocks
1 13
1 17
1 20
2 52
2 64
PLLs LAB Columns LAB Rows
1 24 13
2 26 17
2 32 20
2 48 26
2 64 32
Altera Corporation
5
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Information | Total 30 Pages | |
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