PDF CY7B9910 Data sheet ( Hoja de datos )

Número de pieza	CY7B9910
Descripción	(CY7B9910 / CY7B9920) Low Skew Clock Buffer
Fabricantes	Cypress Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de CY7B9910 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas
No Preview Available ! fax id: 35161CY7B9920 CY7B9910 CY7B9920 Features • All outputs skew <100 ps typical (250 max.) • 15- to 80-MHz output operation • Zero input to output delay • 50% duty-cycle outputs • Outputs drive 50Ω terminated lines • Low operating current • 24-pin SOIC package • Jitter: <200 ps peak to peak, <25 ps RMS • Compatible with Pentium™-based processors Functional Description The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer low-skew system clock distribution. These multiple-output clock drivers optimize the timing of high-performance comput- er systems. Eight individual drivers can each drive terminated transmission lines with impedances as low as 50Ω while deliv- ering minimal and specified output skews and full-swing logic levels (CY7B9910 TTL or CY7B9920 CMOS). The completely integrated PLL allows “zero delay” capability. External divide capability, combined with the internal PLL, allows distribution of a low-frequency clock that can be multiplied by virtu- ally any factor at the clock destination. This facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility. Logic Block Diagram Low Skew Clock Buffer Block Diagram Description Phase Frequency Detector and Filter These two blocks accept inputs from the reference frequency (REF) input and the feedback (FB) input and generate correc- tion information to control the frequency of the Voltage-Con- trolled Oscillator (VCO). These blocks, along with the VCO, form a Phase-Locked Loop (PLL) that tracks the incoming REF signal. VCO The VCO accepts analog control inputs from the PLL filter block and generates a frequency. The operational range of the VCO is determined by the FS control pin. Test Mode The TEST input is a three-level input. In normal system oper- ation, this pin is connected to ground, allowing the CY7B9910/CY7B9920 to operate as explained above. (For testing purposes, any of the three-level inputs can have a re- movable jumper to ground, or be tied LOW through a 100Ω resistor. This will allow an external tester to change the state of these pins.) If the TEST input is forced to its MID or HIGH state, the device will operate with its internal phase-locked loop disconnected, and input levels supplied to REF will directly control all outputs. Relative output to output functions are the same as in normal mode. Pin Configuration TEST FB REF PHASE FREQ FILTER DET FS Voltage Controlled Oscillator Q0 Q1 Q2 Q3 Q4 Q5 Q6 REF VCCQ FS NC VCCQ VCCN Q0 Q1 GND Q2 Q3 VCCN SOIC Top View 1 24 2 23 3 22 4 21 5 20 6 7B9910 19 7 7B9920 18 8 17 9 16 10 15 11 14 12 13 GND TEST NC GND VCCN Q7 Q6 GND Q5 Q4 VCCN FB 7B9910–1 Pentium is a trademark of Intel Corporation. Q7 7B9910–2 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 November 1994 – Revised July 7, 1997 1 page CY7B9910 CY7B9920 Switching Characteristics Over the Operating Range[7] (continued) Parameter fNOM tRPWH tRPWL tSKEW tDEV tPD tODCV tORISE tOFALL tLOCK tJR tJR Description Operating Clock Frequency in MHz FS = LOW[9, 10] FS = MID[9, 10] FS = HIGH[9, 10, 11] REF Pulse Width HIGH REF Pulse Width LOW Zero Output Skew (All Outputs)[13, 14] Device-to-Device Skew[8, 15] Propagation Delay, REF Rise to FB Rise Output Duty Cycle Variation[16] Output Rise Time[17, 18] Output Fall Time[17, 18] PLL Lock Time[19] Cycle-to-Cycle Output Peak to Peak[8] Jitter RMS[8] CY7B9910–7 Min. Typ. Max. 15 30 25 50 40 80 5.0 5.0 0.3 0.75 1.5 –0.7 0.0 +0.7 –1.2 0.0 +1.2 0.15 1.5 2.5 0.15 1.5 2.5 0.5 200 25 CY7B9920–7 Min. Typ. Max. 15 30 Unit MHz 25 50 40 80[12] 5.0 ns 5.0 ns 0.3 0.75 ns 1.5 ns –0.7 0.0 +0.7 ns –1.2 0.0 +1.2 ns 0.5 3.0 5.0 ns 0.5 3.0 5.0 ns 0.5 ms 200 ps 25 ps AC Timing Diagrams REF tPD FB tREF tRPWH tRPWL tODCV tODCV Q OTHER Q tSKEW tSKEW tJR 7B9910–8 5 5 Page

Páginas	Total 7 Páginas
PDF Descargar	[ Datasheet CY7B9910.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
CY7B991	Programmable Skew Clock Buffer	Cypress Semiconductor
CY7B9910	(CY7B9910 / CY7B9920) Low Skew Clock Buffer	Cypress Semiconductor
CY7B9911	High-Speed Low-Voltage Programmable Skew Clock Buffer LV-PSCB	Cypress Semiconductor
CY7B9911V	High-Speed Low-Voltage Programmable Skew Clock Buffer LV-PSCB	Cypress Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar