PDF MN673274 Data sheet ( Hoja de datos )

Número de pieza	MN673274
Descripción	Signal-Processing LSI for Multimedia Camera
Fabricantes	Panasonic
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No Preview Available ! Video Camera LSI MN673274 Signal-Processing IC for Multipurpose Cameras s Overview The MN673274 is designed for surveillance and PC input cameras. In addition to the basic functions of luminance signal and chrominance signal processing, it also integrates microcontroller functions (ALC, AWB, and AGC) and SSG, CG, and I2C-bus circuits on a single chip. s Features • Input: Analog signal (A/D converter input) • Output: Digital output YUV signal: 8 bits Analog outputs Y signal C signal Composite video output RGB outputs • Operating supply voltage: 3.3 V ± 0.3 V • Operating frequency: 9.5 MHz to 28.7 MHz • Main functions • 10-bit A/D converter • 10-bit D/A converter • 2-channel 8-bit D/A converter • Support for analog AGC (NN2038, NN2039) • CG and SSG functions • 510H and 768H (Supports NTSC and PAL ) • Supports progressive scan readout CCDs with complementary color filters for VGA • Supports black-and-white CCD signal processing • CCD white defect/black defect correction circuit • Maximum digital AGC gain: 24 dB • Left/right reversing function • Variable gamma correction (γ = 0.3 to 1) • ZV port conforming mode, BT656 conforming mode • External synchronization support: HD/VD, VD2, Sync., LL mode • On-chip I2C-bus circuit • ELC/AGC (Also supports external AGC) • Two-mode white balance (manual/ATW) with ATW lock function • Automatic OB correction function s Applications • Surveillance cameras, PC cameras 1 1 page Video Camera LSI MN673274 s Pin Descriptions (continued) Pin No. Pin Name I/O Description 36 YUVOE I Digital output system output enable 37 VCSYNCVD O VCSYNC output/VD output (VGA mode: CSYNC, IT mode: register switching) 38 HREFCBLK O HREF output/CBLK output (VGA mode: HREF, IT mode: register switching) 39 SCANT I Test input (Normally connect low) 40 MINTEST I Test input (Normally connect low) 41 FVR I DC level input used for frequency control 42 LPFI I Low-pass filter analog switch input 43 VCXO O Analog switch output - LC oscillator 44 DAVDD2 VDD D/A converter power supply 45 DAVSS2 VSS D/A converter ground 46 GSIG O Video output (composite/G signal) Connect the resistor RL between GSIG and DAVSS2 47 COMP1 I Phase compensation Connect a 1 µF capacitor between COMP1 and DAVDD2 48 IREF1 49 VREF1 I Bias current resistor connection Connect the resistor RIREF between IREGF1 and DAVSS2 I Reference voltage input 50 RSIG O Video output (luminance/R signal) Connect the resistor RL between RSIG and DAVSS1 51 DAVDD1 VDD D/A converter power supply 52 DAVSS1 VSS D/A converter ground 53 BSIG O Video output (chrominance/B signal) Connect the resistor RL between BSIG and DAVSS1 54 COMP23 I Phase compensation Connect a 1 µF capacitor between this pin and DAVDD1 55 IREF23 56 VREF23 I Bias current resistor connection Connect the resistor RIREF between this pin and DAVSS1 I Reference voltage input 57 VREFH I High-level reference voltage input 58 VREFHM I Intermediate reference potential Connect a capacitor between this pin and ADVSS 59 VREFM I Intermediate reference potential Connect a capacitor between this pin and ADVSS 60 ADVSS VSS A/D converter power supply 61 ADVDD VDD A/D converter ground 62 VREFML I Intermediate reference potential Connect a capacitor between this pin and ADVSS 63 VREFL I Low-level reference voltage input 64 VIN I Analog signal input 65 TEST4 I Test input (Normally connect low) 66 TEST3 I Test input (Normally connect low) 67 TEST2 I Test input (Normally connect low) 68 TEST1 I Test input (Normally connect low) 69 TEST0 I Test input (Normally connect low) 70 CCDSEL0 I CCD switching 71 CCDSEL1 I CCD switching 72 CCDSEL2 I CCD switching 5 5 Page Video Camera LSI MN673274 6. D/A Converter VDD = TGVDD = OSCVDD = 3.3 V, ADVDD = DAVDD = 3.3 V, VSS = TGVSS = OSCVSS = ADVSS = DAVSS = 0 V, Ta = 25°C 1) Pins: VREF23, IREF23, COMP23, BSIG, and RSIG Item Symbol Condition Min Typ Max Unit D/A Converter Recommended Operating Conditions Reference voltage VREF RL = 75 Ω RIREF23 = 820 Ω  1.37  V External phase assurance capacitor CCOMP Connect between the COMP23 pin and AVDD.  1.0  µF External output resistors RL Connect these between the  75 Ω BSIG and RSIG pins respectively, and AVSS. External bias current setting resistor RIREF Connect between the IREF23 pin and AVSS.  820  Ω D/A converter characteristics Resolution Nonlinearity error Differential nonlinearity error Full-scale voltage Zero-scale voltage RES INLE DNLE VOFS VOZS RL = 75 Ω VREF23 = 1.37 V RIREF23 = 820 Ω  8 bit   ± 2.5 LSB   ± 2.5 LSB  1.0  V  0 V 2) Pins: VREF1, IREF1, COMP1, and GSIG Item Symbol Condition D/A Converter Recommended Operating Conditions Reference voltage VREF RL = 75 Ω RIREF1 = 1.13 kΩ External phase assurance capacitor External output resistors CCOMP RL Connect between the COMP1 pin and AVDD. Connect between the GSIG pin and AVSS. External bias current setting resistor RIREF Connect between the IREF1 pin and AVSS. D/A converter characteristics Resolution Nonlinearity error Differential nonlinearity error Full-scale voltage Zero-scale voltage RES INLE DNLE VOFS VOZS RL = 75 Ω VREF1 = 1.5 V RIREF1 = 1.13 kΩ Min Typ Max Unit  1.5  V  1.0  µF  75  Ω  1.13  kΩ   10 bit   ± 2.5 LSB   ± 2.5 LSB  1.0  V  0 V 11 11 Page

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