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What is ID82C284?

This electronic component, produced by the manufacturer "Intersil Corporation", performs the same function as "Clock Generator and Ready Interface for 80C286 Processors".


ID82C284 Datasheet PDF - Intersil Corporation

Part Number ID82C284
Description Clock Generator and Ready Interface for 80C286 Processors
Manufacturers Intersil Corporation 
Logo Intersil Corporation Logo 


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82C284
March 1997
Clock Generator and Ready Interface
for 80C286 Processors
Features
• Generates System Clock for 80C286 Processors
• Generates System Reset Output from Schmitt
Trigger Input
- Improved Hysteresis
• Uses Crystal or External Signal for Frequency Source
• Dynamically Switchable between Two Input
Frequencies
• Provides Local READY and MULTIBUS® READY
Synchronization
• Static CMOS Technology
• Single +5V Power Supply
• Available in 18 Lead CerDIP Package
Description
The Intersil 82C284 is a clock generator/driver which
provides clock signals for 80C286 processors and support
components. It also contains logic to supply READY to the
CPU from either asynchronous or synchronous sources and
synchronous RESET from an asynchronous input with
hysteresis.
Ordering Information
PART NUMBER
CD82C284-12
ID82C284-10
ID82C284-12
TEMP. RANGE
0oC to +70oC
-40oC to +85oC
-40oC to +85oC
PACKAGE
PKG.
NO.
18 Ld CERDIP F18.3
18 Ld CERDIP F18.3
18 Ld CERDIP F18.3
Pinout
82C284 (CERDIP)
TOP VIEW
ARDY 1
SRDY 2
SRDYEN 3
READY 4
EFI 5
F/C 6
X1 7
X2 8
GND 9
18 VCC
17 ARDYEN
16 S1
15 S0
14 NC
13 PCLK
12 RESET
11 RES
10 CLK
Functional Diagram
RES
X1
X2
EFI
F/C
ARDYEN
ARDY
SRDYEN
SRDY
S1
S0
RESET
SYNCHRONIZER
XTAL
OSC
MUX
SYNCHRONIZER
READY LOGIC
PCLK GENERATOR
RESET
CLK
READY
PCLK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
MULTIBUS® is a patented Intel bus.
1
File Number 2966.1

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ID82C284 equivalent
82C284
LOW to HIGH input transition voltage. As long as the slope of
the RES input voltage remains in the same direction (increas-
ing or decreasing) around the RES input transition voltage, the
RESET output will make a single transition.
VCC
1N914
47
10k
82C284
11
RES
+
10µF
FIGURE 3. TYPICAL RC RES TIMING CIRCUIT
Ready Operation
The 82C284 accepts two ready sources for the system ready
signal which terminates the current bus cycle. Either a synchro-
nous (SRDY) or asynchronous ready (ARDY) source may be
used. Each ready input has an enable (SRDYEN and
ARDYEN) for selecting the type of ready source required to ter-
minate the current bus cycle. An address decoder would nor-
mally select one of the enable inputs.
READY is enabled (LOW), if either SRDY + SRDYEN = 0 or
ARDY + ARDYEN = 0 when sampled by the 82C284 READY
generation logic. READY will remain active for at least two CLK
cycles.
The READY output has an open-drain driver allowing other
ready circuits to be wired with it, as shown in Figure 4. The
READY signal of an 80C286 system requires an external
pull-up resistor. To force the READY signal inactive (HIGH)
at the start of a bus cycle, the READY output floats when
either S1 or S0 are sampled LOW at the falling edge of CLK.
Two system clock periods are allowed for the pull-up resistor
to pull the READY signal to VlH. When RESET is active,
READY is forced active one CLK later (see Waveforms).
7
X1
10
CLK
CLK
VCC
80C286
8 X2
CPU OR
C1
82C284
SUPPORT
COMPONENT
4
6
READY
18
READY
F/C VCC
VCC
DECOUPLING
CAPACITOR
FIGURE 4. RECOMMENDED CRYSTAL AND READY
CONDITIONS
Figure 5 illustrates the operation of SRDY and SRDYEN.
These inputs are sampled on the falling edge of CLK when
S1 and S0 are inactive and PCLK is HIGH. READY is forced
active when both SRDY and SRDYEN are sampled as LOW.
Figure 6 shows the operation of ARDY and ARDYEN These
inputs are sampled by an internal synchronizer at each fall-
ing edge of CLK. The output of the synchronizer is then sam-
pled when PCLK is HIGH. If the synchronizer resolved both
the ARDY and ARDYEN as active, the SRDY and SRDYEN
inputs are ignored. Either ARDY or ARDYEN must be HIGH
at the end of TS, therefore, at least one wait state is required
when using the ARDY and ARDYEN inputs as a basis for
generating READY.
READY remains active until either S1 or S0 are sampled
LOW, or the ready inputs are sampled as inactive.
5


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Part Details

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Featured Datasheets

Part NumberDescriptionMFRS
ID82C284The function is Clock Generator and Ready Interface for 80C286 Processors. Intersil CorporationIntersil Corporation

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