|
|
PDF MTV004 Data sheet ( Hoja de datos )
| Número de pieza | MTV004 | |
| Descripción | On-Screen Display Shrink Version | |
| Fabricantes | Myson | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MTV004 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
|
No Preview Available !
MYSON
TECHNOLOGY
MTV004
On-Screen Display Shrink Version
FEATURES
• On-chip phase lock loop circuitry for multi-sync operation.
• Horizontal input up to 100 KHz.
• 273-byte display registers to control full screen display.
• Full screen display consisting of 10 rows by 24 characters.
• 128 alphanumeric characters or graphic symbols built in character ROM.
• 12 x 16 dot matrix per character.
• Character by character color selection.
• 4 color selections in a total of 8 color combinations per row.
• 4-character size options available by doubling character height and/or width.
• Programmable positioning for display screen center.
• Character bordering and shadowing.
• Programmable vertical character height for multi-sync operation.
• Multi-level windowing effect.
• Half tone and fast blanking output.
• Compatible with both SPI bus and I2C interface through pin selection.
• 16-pin PDIP package.
GENERAL DESCRIPTION
MTV004 is designed for use in monitor applications to display the built-in characters or symbols onto the
monitor screen. The display operation is enabled by transferring data and control information in the
microcontroller to RAM through a serial data interface. It can execute the full screen display automatically as
well as some specific functions such as character bordering, shadowing, double height, double width and color
control, frame positioning, vertical display height, and windowing effect.
BLOCK DIAGRAM
6
SSB
8
SCK
7
SDA
VFLB
10
SERIAL DATA
INTERFACE
8DATA
DAEN
2RAEN,CAEN
RAEN,CAEN 2 ADDRESS BUS
ADMINISTRATOR
ARWDB
9 DADDR
5 WADDR
DHOR
DVERT
CH 6
CHS
VERTD 6
VERTICAL
CONTROL
LOGIC
4 LP
NROW
DVERT
CWS
CHS
DISPLAY
REGISTERS
(RAM)
12C(R,G,B)*4
CCS0
7 CRADDR
LP1/2 2
VCLK
4
LP
CHARACTER ROMS
NROW
12-BIT SHIFT
REGISTERS
CWS
BSEN
SHADOW
LUMA
BORDER
DATA 8
WACTIVE
CCS1
CH 6
WINDOWS &
FRAME
CONTROL
BSEN
SHADOW
6VERTD
5HORD
OSDENB
9 VDD
16 VSS
4 VDDA
1 VSSA
5
HFLB
RP
VCO
2
3
HORD 5
HORIZONTAL
2LD1/2
DHOR
CONTROL LOGIC ARWDB
PHASE LOCK LOOP VCLK
C(R,G,B)*4 12
WACTIVE
CCS1
CCS0
COLOR
ENCODER
15
ROUT
14
GOUT
13
BOUT
12
FBKG
11
HTONE
This data sheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
MTV004 Revision 4.0 06/24/1999
1/9
1 page  
MYSON
TECHNOLOGY
MTV004
The vertical display center for a full-screen display may be figured out according to the information of the
vertical starting position register (VERTD) and VFLB input. The vertical delay, starting from the falling edge of
VFLB, is calculated using the following equation:
Vertical delay time = (VERTD * 4 + 1) * H
H = 1 horizontal line display time
Table 2. Repeat Line Character Weight
CH5 - CH0
CH5,CH4=11
CH5,CH4=10
CH5,CH4=0x
CH3=1
CH2=1
CH1=1
CH0=1
Repeat Line Weight
(+16)*3
(+16)*2
+16
+8
+4
+2
+1
Table 3. Repeat Line Character Number
Repeat Line
Weight
+1
+2
+4
+8
+16
Repeat Line #
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
--------v-- - - - - -
----v------ - v - - -
--v---v---v - - - v -
-v-v-v-v-v- v - v - v
vvvvvvvvvvv v v v v v
Note: " v " means the nth line in the character would be repeated once, while "-" means the nth line in the
character would not be repeated.
3.4 Horizontal Control Logic
The horizontal control logic is used to generate control timing for the horizontal display based on the double
character width bit (CWS), horizontal positioning register (HORD) and HFLB input. A horizontal display line
consists of 384 dots, which include 288 dots for 24 display characters and 96 dots for the remaining blank
region. The horizontal delay starting from the HFLB falling edge is calculated using the following equation:
horizontal delay time = (HORD * 6 + 61)* P - phase error detection pulse width
P= 1 pixel display time = 1 horizontal display time / 384
3.5 Phase Lock Loop (PLL)
On-chip PLL generates system clock timing (VCLK) by tracking the input HFLB. The frequency of VCLK is
determined using the following equation:
VCLK = HFLB Freq.* 384 ,
The frequency ranges from 3.84MHz to 38.4MHz. See Table 4.
Table 4. Frequency Range
HFLB
10KHz to 100KHz
VCLK
3.84MHz to 38.4MHz
MTV004 Revision 4.0 06/24/1999
5/9
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MTV004.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MTV003 | Microprocessor Compatible Monitor Controller | Myson |
| MTV003N | Microprocessor Compatible Monitor Controller | Myson |
| MTV004 | On-Screen Display Shrink Version | Myson |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |