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PDF 24C08W6 Data sheet ( Hoja de datos )
| Número de pieza | 24C08W6 | |
| Descripción | M24C08W6 | |
| Fabricantes | ST Microelectronics | |
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M24C16, M24C08
M24C04, M24C02, M24C01
16/8/4/2/1 Kbit Serial I²C Bus EEPROM
s Two Wire I2C Serial Interface
Supports 400 kHz Protocol
www.DataSheet4Us.coSmingle Supply Voltage:
– 4.5V to 5.5V for M24Cxx
– 2.5V to 5.5V for M24Cxx-W
– 1.8V to 3.6V for M24Cxx-R
s Hardware Write Control
s BYTE and PAGE WRITE (up to 16 Bytes)
s RANDOM and SEQUENTIAL READ Modes
s Self-Timed Programming Cycle
s Automatic Address Incrementing
s Enhanced ESD/Latch-Up Behavior
s 1 Million Erase/Write Cycles (minimum)
s 40 Year Data Retention (minimum)
DESCRIPTION
These I2C-compatible electrically erasable
programmable memory (EEPROM) devices are
organized as 2048/1024/512/256/128 x 8 bit
(M24C16, M24C08, M24C04, M24C02, M24C01),
and operate with a power supply down to 2.5 V (for
the -W version of each device), and down to 1.8 V
(for the -R version of each device).
The M24C16, M24C08, M24C04, M24C02,
M24C01 are available in Plastic Dual-in-Line,
Plastic Small Outline and Thin Shrink Small
Outline packages. The M24C16-R is also
available in a chip-scale (SBGA) package.
Table 1. Signal Names
E0, E1, E2
Chip Enable Inputs
SDA
Serial Data/Address Input/
Output
SCL
Serial Clock
WC Write Control
VCC
VSS
Supply Voltage
Ground
8
1
PSDIP8 (BN)
0.25 mm frame
8
1
TSSOP8 (DW)
169 mil width
8
1
SO8 (MN)
150 mil width
SBGA
SBGA5 (EA)
75 mil width
Figure 1. Logic Diagram
VCC
3
E0-E2
SCL
WC
M24Cxx
SDA
VSS
AI02033
May 2000
1/20
1 page  
M24C16, M24C08, M24C04, M24C02, M24C01
Table 3. Device Select Code 1
Device Type Identifier
Chip Enable
b7 b6 b5 b4 b3 b2
M24C01 Select Code
1
0
1
0 E2 E1
M24C02 Select Code
1
0
1
0 E2 E1
M24C04 Select Code
1
0
1
0 E2 E1
M24C08 Select Code
1
0
1
0 E2 A9
M24C16 Select Code
1
0
1
0 A10
www.DataSheet4UN.cootem: 1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
3. A10, A9 and A8 represent high significant bits of the address.
A9
b1
E0
E0
A8
A8
A8
RW
b0
RW
RW
RW
RW
RW
Write Control (WC)
The hardware Write Control pin (WC) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC=VIL) or disable (WC=VIH)
write instructions to the entire memory area. When
unconnected, the WC input is internally read as
VIL, and write operations are allowed.
When WC=1, Device Select and Address bytes
are acknowledged, Data bytes are not
acknowledged.
Please see the Application Note AN404 for a more
detailed description of the Write Control feature.
DEVICE OPERATION
The memory device supports the I2C protocol.
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note
AN1001. Any device that sends data on to the bus
is defined to be a transmitter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is known as the master,
and the other as the slave. A data transfer can only
be initiated by the master, which will also provide
the serial clock for synchronization. The memory
device is always a slave device in all
communication.
Start Condition
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device
continuously monitors (except during a
programming cycle) the SDA and SCL lines for a
START condition, and will not respond unless one
is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates
communication between the memory device and
the bus master. A STOP condition at the end of a
Read command, after (and only after) a NoAck,
forces the memory device into its standby state. A
STOP condition at the end of a Write command
triggers the internal EEPROM write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a
successful byte transfer. The bus transmitter,
whether it be master or slave, releases the SDA
bus after sending eight bits of data. During the 9th
Table 4. Operating Modes
Mode
RW bit
Current Address Read
1
Random Address Read
0
1
Sequential Read
1
Byte Write
0
Page Write
Note: 1. X = VIH or VIL.
0
WC 1
X
X
X
X
VIL
VIL
Bytes
1
1
≥1
1
≤ 16
Initial Sequence
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
START, Device Select, RW = ‘0’
5/20
5 Page 
M24C16, M24C08, M24C04, M24C02, M24C01
Table 5B. DC Characteristics1
(TA = –40 to 125 °C; VCC = 4.5 to 5.5 V)
Symbol
Parameter
ILI Input Leakage Current (SCL, SDA)
ILO Output Leakage Current
ICC Supply Current
ICC1 Supply Current (Stand-by)
www.DataSheet4U.comVIL
VIH
Input Low Voltage (E0, E1, E2, SCL, SDA)
Input High Voltage (E0, E1, E2, SCL, SDA)
VIL Input Low Voltage (WC)
VIH Input High Voltage (WC)
VOL Output Low Voltage
Note: 1. This is preliminary data.
Test Condition
0 V ≤ VIN ≤ VCC
0 V ≤ VOUT ≤ VCC, SDA in Hi-Z
VCC=5V, fc=400kHz (rise/fall
time < 30ns)
VIN = VSS or VCC , VCC = 5 V
IOL = 3 mA, VCC = 5 V
Min.
– 0.3
0.7VCC
– 0.3
0.7VCC
Max.
±2
±2
Unit
µA
µA
3 mA
5
0.3 VCC
VCC+1
0.5
VCC+1
0.4
µA
V
V
V
V
V
Table 6A. AC Characteristics
M24C16, M24C08, M24C04, M24C02, M24C01
Symbol Alt.
Parameter
VCC=4.5 to 5.5 V VCC=2.5 to 5.5 V VCC=1.8 to 3.6 V
TA=0 to 70°C or TA=0 to 70°C or TA=0 to 70°C or Unit
–40 to 85°C
–40 to 85°C
–40 to 85°C4
Min Max Min Max Min Max
tCH1CH2
tR Clock Rise Time
300 300 300 ns
tCL1CL2
tF Clock Fall Time
300 300 300 ns
tDH1DH2 2 tR SDA Rise Time
20 300 20 300 20 300 ns
tDL1DL2 2
tF SDA Fall Time
20 300 20 300 20 300 ns
tCHDX 1 tSU:STA Clock High to Input Transition
600
600
600 ns
tCHCL tHIGH Clock Pulse Width High
600
600
600 ns
tDLCL tHD:STA Input Low to Clock Low (START)
600
600
600 ns
tCLDX tHD:DAT Clock Low to Input Transition
0
0
0 µs
tCLCH tLOW Clock Pulse Width Low
1.3
1.3
1.3 µs
tDXCX
tSU:DAT
Input Transition to Clock
Transition
100
100
100 ns
tCHDH tSU:STO Clock High to Input High (STOP) 600 600 600 ns
tDHDL
tBUF
Input High to Input Low (Bus
Free)
1.3
1.3
1.3 µs
tCLQV 3
tAA Clock Low to Data Out Valid
200 900 200 900 200 900 ns
tCLQX
tDH
Data Out Hold Time After Clock
Low
200
200
200 ns
fC fSCL Clock Frequency
400 400 400 kHz
tW tWR Write Time
5 10 10 ms
Note: 1. For a reSTART condition, or following a write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. This is preliminary data.
11/20
11 Page | ||
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