PDF CY28400 Data sheet ( Hoja de datos )

Número de pieza	CY28400
Descripción	100-MHz Differential Buffer for PCI Express and SATA
Fabricantes	Cypress Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de CY28400 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas
No Preview Available ! CY28400 100-MHz Differential Buffer for PCI Express and SATA Features • CK409 or CK410 companion buffer • Four differential 0.7v clock pairs • Individual OE controls • Low CTC jitter (< 50 ps) • Programmable bandwidth • SRC_STOP# power management control • SMBus Block/Byte/Word Read and Write support • 3.3V operation • PLL Bypass-configurable • Divide by 2 programmable outputs • 28-pin SSOP package Functional Description The CY28400 is a differential buffer and serves as a companion device to the CK409 or CK410 clock generator. The device is capable of distributing the Serial Reference Clock (SRC) in PCI Express and SATA implementations. Block Diagram OE_(1,6) SRC_STOP# PWRDWN# SCLK SDATA PLL/BYPASS# SRCT_IN SRCC_IN HIGH_BW# Output Control SMBus Controller DIFT1 DIFC1 DIFT2 DIFC2 Output Buffer DIFT5 DIFC5 DIV PLL DIFT6 DIFC6 Pin Configuration VDD SRCT_IN SRCC_IN VSS VDD DIFT1 DIFC1 OE_1 DIFT2 DIFC2 VDD PLL/BYPASS# SCLK SDATA 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 28 SSOP VDD_A VSS_A IREF VSS VDD DIFT6 DIFC6 0E_6 DIFT5 DIFC5 VDD HIGH_BW# SRC_STOP# PWRDWN# Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-07591 Rev. Revised November 24, 2003 1 page CY28400 Byte 4: Vendor ID Register Bit @Pup 70 60 50 40 31 20 10 00 Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description Byte 5: Control Register 5 Bit @Pup 70 60 50 40 30 20 10 00 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description PWRDWN# Clarification[1] PWRDWN#—Assertion The PWRDWN# pin is used to shut off all clocks cleanly and instruct the device to evoke power savings mode. Additionally, PWRDWN# should be asserted prior to shutting off the input clock or power to ensure all clocks shut down in a glitch-free manner. PWRDWN# is an asynchronous active low input. This signal is synchronized internal to the device prior to powering down the clock buffer. PWRDWN# is an asynchronous input for powering up the system. When PWRDWN# is asserted low, all clocks will be held high or three-stated (depending on the state of the control register drive mode and OE bits) prior to turning off the VCO. All clocks will start and stop without any abnormal behavior and must meet all AC and DC parameters. This means no glitches, frequency shifting or amplitude abnor- malities among others. When PWRDWN# is sampled low by two consecutive rising edges of DIFC, all DIFT outputs will be held high or three-stated (depending on the state of the control register drive mode and OE bits) on the next DIFC high to low transition. When the SMBus power-down drive mode bit is programmed to ‘0’, all clock outputs will be held with the DIFT pin driven high at 2 x Iref and DIFC three-state. However, if the control register PWRDWN# drive mode bit is programmed to ‘1’, then both DIFT and the DIFC are three-stated. PWRDWN# DIFT DIFC Figure 1. PWRDWN# Assertion Diagram Note: 1. Disabling of the SRCT_IN input clock prior to assertion of PWRDWN# is an undefined mode and not recommended. Operation in this mode may result in glitches excessive frequency shifting. Document #: 38-07591 Rev. Page 5 of 14 5 Page CY28400 AC Electrical Specification (continued) Parameter Description VOX ∆VOX VOVS Crossing Point Voltage at 0.7V Swing Vcross Variation over all edges Maximum Overshoot Voltage Condition VUDS Minimum Undershoot Voltage VRB Ring Back Voltage Measured SE tPD(PLL) Input to output skew in PLL mode Measured at crossing point VOX tPD(NONPLL) Input to output skew in Non - PLL mode Measured at crossing point VOX Min. 250 – – – 0.2 – 2.5 D IF T 33Ω T PCB 4 9 .9 Ω M easurem ent P o in t 2pF D IF C IR E F 33Ω T PCB 4 9 .9 Ω M easurem ent P o in t 2pF 475Ω T ra c e Im p e d a n c e M e a s u re d D iffe re n tia lly Figure 8. Differential Clock Termination Switching Waveforms Max. 550 140 VHIGH + 0.3 –0.3 N/A ±250 6.5 Unit mv mV V V V ps ns VOH = 0.525V VCROSS TRise (CLOCK) CLOCK# CLOCK VOL = 0.175V TFall (CLOCK) Figure 9. Single-Ended Measurement Points for TRise and TFall Document #: 38-07591 Rev. ** Page 11 of 14 11 Page

Páginas	Total 14 Páginas
PDF Descargar	[ Datasheet CY28400.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
CY28400	100-MHz Differential Buffer for PCI Express and SATA	Cypress Semiconductor
CY28401	100-MHz Differential Buffer for PCI Express and SATA	Cypress Semiconductor
CY28404	CK409-COMPLIANT CLOCK SYNTHESIZER	Cypress Semiconductor
CY28405	CK409-Compliant Clock Synthesizer	Cypress Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar