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PDF CXD3048R Data sheet ( Hoja de datos )
| Número de pieza | CXD3048R | |
| Descripción | CD Digital Signal Processor | |
| Fabricantes | Sony Electronics | |
| Logotipo |  |
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CXD3048R
CD Digital Signal Processor with Built-in Digital Servo +
Shock-proof Memory Controller + Digital High & Bass Boost
Description
The CXD3048R is a digital signal processor LSI for CD
players. This LSI incorporates a digital servo, high & bass
boost, shock-proof memory controller, 1-bit DAC and
analog low-pass filter.
120 pin LQFP (Plastic)
Features
• All digital signal processing during playback is
performed with a single chip
• Highly integrated mounting possible due to a built-in RAM
Digital Signal Processor (DSP) Block
• Supports CAV (Constant Angular Velocity) playback
• Frame jitter free
• 0.5× to 4× speed continuous playback possible
• Allows relative rotational velocity readout
• Wide capture range playback mode
• Spindle rotational velocity following method
• Supports 1× to 4× speed playback
• Supports variable pitch playback
• The bit clock, which strobes the EFM signal, is
generated by the digital PLL.
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error correction
C1: double correction, C2: quadruple correction
Supported during 4× speed playback
• Noise reduction during track jumps
• Auto zero-cross mute
• Subcode demodulation and subcode-Q data error
detection
• Digital spindle servo
• 16-bit traverse counter
• Asymmetry correction circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a new
CPU interface
• Servo auto sequencer
• Fine search performs track jumps with high accuracy
• Digital audio interface outputs
• Digital level meter, peak meter
• Bilingual compatible
• VCO control mode
• CD TEXT data demodulation
• Digital Out can be generated from the audio serial
input. (also supported after shock-proof and digital
bass boost processing, subcode-Q addition function)
Digital Servo (DSSP) Block
• Microcomputer software-based flexible servo control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment functions
• Surf jump function supporting micro two-axis
• Tracking filter: 6 stages
Focus filter: 5 stages
Digital Filter, DAC and Analog Low-pass Filter Blocks
• Digital dynamic bass boost and high boost
Bass Boost: 4th-order IIR 24dB/Oct
+10dB/+14dB/+18dB/+22dB
High Boost: Second-order IIR 12dB/Oct
+4dB/+6dB/+8dB/+10dB
• Independent turnover frequency selection possible
Bass Boost: 125Hz/160Hz/200Hz
High Boost: 5kHz/7kHz
• Digital dynamics (compressor)
Volume increased by +5dB at low level
• 8× oversampling digital filter
(attenuation: 61dB, ripple within band: ±0.0075dB)
• Digital signal output possible after boost
• Serial data format selectable from (output) 20 bits/
18 bits/16 bits (rearward truncation, MSB first)
• Digital attenuation: – ∞, –60 to +6dB, 2048 steps (linear)
• Soft mute
• Digital de-emphasis
• High-cut filter
Applications
CD players
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage VDD, AVDD Vss – 0.5 to +3.5 V
• Input voltage VI
Vss – 0.3 to VDD + 0.3 V
• Output voltage VO
Vss – 0.3 to VDD + 0.3 V
• Storage temperature Tstg
–55 to +150
°C
• Supply voltage difference
AVSS – VSS
–0.3 to +0.3
V
AVDD – VDD –0.3 to +0.3V (AVDD < 1.7V)
AVDD – VDD –0.3 to +1.0V (AVDD = 1.7 to 2.7V)
Recommended Operating Conditions
• Supply voltage
VDD, AVDD0, 3, XVDD
1.7 to 2.7
AVDD1, 2, DVDD
VDD to 2.7
• Operating temperature Topr
–20 to +75
V
V
°C
Shock-proof Memory Controller Block
• Supports an external 4M-bit/16M-bit DRAM
• Time axis-based data linking
• ADPCM compression method (uncompressed/4 bits/
6 bits/8 bits)
I/O Pin Capacitance
• Input capacitance
CI
• Output capacitance CO
Note) Measurement conditions
7 (max.)
7 (max.)
VDD = VI = 0V
fM = 1MHz
pF
pF
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E02653A37
1 page  
CXD3048R
Power Pin
supply No.
Symbol
I/O Value
Description
32 R4M
O
1, 0
Microcomputer clock output. R8M and C4M are output by switching with
the command.
33 Vss0 — — Digital GND.
34 SQCK I
SQSO readout clock input.
35 SCLK I
SENS serial data readout clock input.
36 SQSO
Digital
37 XEMP
O
1, 0
Subcode Q 80-bit and PCM peak and level data output. CD TEXT data
output.
O 1, 0 DRAM readout prohibited signal.
38 XWIH O 1, 0 Write to DRAM prohibited signal.
39 SBSO O 1, 0 Subcode P to W serial output.
40 EXCK I
SBSO readout clock input.
41 XTSL
I
Crystal selection input. Low when the crystal is 16.9344MHz; high when
the crystal is 33.8688MHz.
42 HVSS — — Headphone GND.
43 HPL
H/P
44 HPR
O 1, 0 Lch headphone PDM output.
O 1, 0 Rch headphone PDM output.
45 HVDD — — Headphone power supply.
46 XVDD
Master clock power supply.
47 XTAI
X'tal
48 XTAO
I
O
Crystal oscillation circuit input. The master clock is externally input from
this pin.
Crystal oscillation circuit output.
49 XVSS
Master clock GND.
50 AVDD1 — — Analog power supply.
51 AOUT1 O Analog Lch analog output.
Lch
52 VREFL O Analog Lch reference voltage.
53 AVSS1 — — Analog GND.
54 AVSS2 — — Analog GND.
55 VREFR O Analog Rch reference voltage.
Rch
56 AOUT2 O Analog Rch analog output.
57 AVDD2 — — Analog power supply.
58 TES1
I
Test pin. Normally GND.
59 TEST I
Test pin. Normally GND.
60 VSS1
— — Digital GND.
61 LRMU
Digital
62 DOUT
O
1, 0
OR signal output of Lch, Rch "0" detection flag (AND output) and SYSM.
Only "0" detection flag is output by switching with the command.
O 1, 0 Digital Out output.
63 ATSK I/O 1, 0 Anti-shock input/output.
64 DFCT I/O 1, 0 Defect signal input/output.
65 FOK I/O 1, 0 Focus OK signal input/output.
–5–
5 Page 
2. AC Characteristics
(1) XTAI pin
(a) When using self-excited oscillation
(VDD = AVDD = 1.8 ± 0.1V and 2.5 ± 0.2V, Vss = AVss = 0V, Topr = –20 to +75°C)
Item
Oscillation
frequency
Symbol Min. Typ. Max. Unit
fMAX
7
34 MHz
(b) When inputting pulses to XTAI pin
(VDD = AVDD = 1.8 ± 0.1V and 2.5 ± 0.2V, Vss = AVss = 0V, Topr = –20 to +75°C)
Item Symbol Min. Typ. Max. Unit
High level pulse
width
tWHX
13
500 ns
Low level pulse
width
tWLX
13
500 ns
Pulse cycle
tCX
26
1000 ns
Input high level VIHX
0.7VDD
V
Input low level
Rise time,
fall time
VILX
tR, tF
0.2VDD V
10 ns
tCX
tWHX
tWLX
XTAI
VIHX
VIHX × 0.9
VDD/2
tR tF
VIHX × 0.1
VILX
Note) When the pulse is input to the XTAI pin, be sure to input it via the capacitor.
– 11 –
CXD3048R
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXD3048R.PDF ] | |
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