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PM49FL002 Datasheet PDF - Programmable Microelectronics

Part Number PM49FL002
Description 2 Mbit / 4 Mbit 3.3 Volt-only Fimware Hub / LPC Flash Memory
Manufacturers Programmable Microelectronics 
Logo Programmable Microelectronics Logo 

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PMC
Pm49FL002 / Pm49FL004
2 Mbit / 4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory
FEATURES
• Single Power Supply Operation
- Low voltage range: 3.0 V - 3.6 V
• Standard Intel Firmware Hub/LPC Inter-
face
- Read compatible to Intel® 82802 Firmware
Hub devices
- Conforms to Intel LPC Interface Specification
Revision 1.1
• Memory Configuration
- Pm49FL002: 256K x 8 (2 Mbit)
- Pm49FL004: 512K x 8 (4 Mbit)
Cost Effective Sector/Block Architecture
- Pm49FL002: Sixty-four uniform 4 Kbyte
sectors, or sixteen uniform 16 Kbyte blocks
(sector group)
- Pm49FL004: One hundred and twenty-eight
uniform 4 Kbyte sectors, or eight uniform 64
Kbyte blocks (sector group)
Top Boot Block
- Pm49FL002: 16 Kbyte top Boot Block
- Pm49FL004: 64 Kbyte top Boot Block
Automatic Erase and Program Operation
- Build-in automatic program verification for
extended product endurance
- Typical 25 µs/byte programming time
- Typical 50 ms sector/block/chip erase time
Two Configurable Interfaces
- In-System hardware interface: Auto detection
of Firmware Hub (FWH) or Low Pin Count
(LPC) memory cycle for in-system read and
write operations
- Address/Address-Multiplexed (A/A Mux)
interface for programming on EPROM Pro-
grammers during manufacturing
Firmware HUB (FWH)/Low Pin Count
(LPC) Mode
- 33 MHz synchronous operation with PCI bus
- 5-signal communication interface for in-
system read and write operations
- Standard SDP Command Set
- Data# Polling and Toggle Bit features
- Register-based read and write protection for
each block (FWH mode only)
- 4 ID pins for multiple Flash chips selection
(FWH mode only)
- 5 GPI pins for General Purpose Input Register
- TBL# pin for hardware write protection to Boot
Block
- WP# pin for hardware write protection to whole
memory array except Boot Block
Address/Address Multiplexed (A/A Mux)
Mode
- 11-pin multiplexed address and 8-pin data I/O
interface
- Supports fast programming on EPROM
programmers
- Standard SDP Command Set
- Data# Polling and Toggle Bit features
Lower Power Consumption
- Typical 2 mA active read current
- Typical 7 mA program/erase current
High Product Endurance
- Guarantee 100,000 program/erase cycles per
single sector (preliminary)
- Minimum 20 years data retention
Compatible Pin-out and Packaging
- 32-pin (8 mm x 14 mm) VSOP
- 32-pin PLCC
- Optional lead-free (Pb-free) package
Hardware Data Protection
Programmable Microelectronics Corp.
PMC and P-Flash are registered trademark of Programmable Microelectronics Corporation.
Intel is a registered trademark of Intel Corporation.
1
Issue Date: December, 2003 Rev:1.4

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PM49FL002 equivalent
PMC
PIN DESCRIPTIONS
Pm49FL002 / 004
SYMBOL
A[10:0]
R/C#
I/O[7:0]
WE#
OE#
IC
RST#
INIT#
GPI[4:0]
TBL#
WP#
FWH[3:0]
FWH4
LAD[3:0]
LFRAME#
CLK
ID[3:0]
VCC
GND
NC
RES
TYPE
I
I
I/O
I
I
I
I
I
I
I
I
I/O
I
I/O
I
I
I
Interface
PP FWH LPC
DESCRIPTION
Address Inputs: For inputing the multiplex addresses and commands in
X PP mode. Row and column addresses are latched during a read or
write cycle controlled by R/C# pin.
Row/Column Select: To indicate the row or column address in PP
X mode. When this pin goes low, the row address is latched. When this
pin goes high, the column address is latched.
Data Inputs/Outputs: Used for A/A Mux mode only, to input
X command/data during write operation and to output data during read
operation. The data pins float to tri-state when OE# is disabled.
X Write Enable: Activate the device for write operation. WE# is active low.
X
Output Enable: Control the device's output buffers during a read cycle.
OE# is active low.
Interface Configuration Select: This pin determines which mode is
selected. When pulls high, the device enters into A/A Mux mode. When
X X X pulls low, FWH/LPC mode is selected. This pin must be setup during
power-up or system reset, and stays no change during operation. This
pin is internally pulled down with a resistor between 20-100 KΩ.
X X X Reset: To reset the operation of the device and return to standby mode.
X
X
Initialize: This is a second reset pin for in-system use. INIT# or RST# pin
pulls low will initiate a device reset.
FWH/LPC General Purpose Inputs: Used to set the GPI_REG for
system design purpose only. The value of GPI_REG can be read
X
X
through FWH interface. These pins should be set at desired state
before the start of the PCI clock cycle for read operation and should
remain no change until the end of the read cycle. Unused GPI pins must
not be floated.
Top Block Lock: When pulls low, it enables the hardware write protection
X X for top boot block. When pulls high, it disables the hardware write
protection.
Write Protect: When pulls low, it enables the hardware write protection
X X to the memory array except the top boot block. When pulls high, it
disables hardware write protection.
X
FWH Address and Data: The major I/O pins for transmitting data,
addresses and command code in FWH mode.
X
FWH Input: To indicate the start of a FWH memory cycle operation.
Also used to abort a FHW memory cycle in progress.
X
LPC Address and Data: The major I/O pins for transmitting data,
addresses and command code in LPC mode.
X
LPC Frame: To indicate the start of a LPC memory cycle operation.
Also used to abort a LPC memory cycle in progress.
X
X
FWH/LPC Clock: To provide a synchronous clock for FWH and LPC
mode operations.
Identification Inputs: These four pins are part of the mechanism that
allows multiple FWH devices to be attached to the same bus. The
X
strapping of these pins is used to identify the component. The boot
device must have ID[3:0] = 0000b and it is recommended that all
subsequent devices should use sequential up-count strapping. These
pins are internally pulled-down with a resistor between 20-100 KΩ.
X X X Device Power Supply
X X X Ground
X X X No Connection
X X Reserved: Reserved function pins for future use.
Note: I = Input, O = Output
Programmable Microelectronics Corp. 5 Issue Date: December, 2003 Rev: 1.4


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