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PDF STLC5432 Data sheet ( Hoja de datos )
| Número de pieza | STLC5432 | |
| Descripción | 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE | |
| Fabricantes | ST Microelectronics | |
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STLC5432
2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE
PRELIMINARY DATA
ONE CHIP SOLUTION FROM PCM BUS TO
TRANSFORMER (CEPT STANDARD)
ISDN PRIMARY ACCESS CONTROLLER
(COMPATIBLE WITH ETSI, OPTION 1 AND 2)
HDB3/BIN ENCODER AND DECODER ON
CHIP
MULTIFRAME STRUCTURE HANDLING
BUILT IN CRC4
EASY LINK TO ST5451/MK50H25/MK5027
LINK CONTROLLERS.
DATA RATE: 2048, 4096 AND 8192 Kb/s FOR
MULTIPLEXED APPLICATIONS
FOUR LOOPBACK MODES FOR TESTING
PSEUDO RANDOM SEQUENCE GENER-
ATOR AND ANALYZER FOR ON-LINE, OFF-
LINE AND AUTOTEST
CLOCK RECOVERY CIRCUITRY ON CHIP
64 BYTE ELASTIC MEMORY FOR TIME
COMPENSATION AND AUTOMATIC FRAME
AND SUPERFRAME ALIGNMENT
32 ON CHIP REGISTERS FOR CONFIGURA-
TIONS, TESTING, ALARMS, FAULT AND ER-
ROR RATE CONTROL.
AUTO ADAPTATIVE DETECTION THRESH-
OLD
AUTOMATIC EQUALIZER OPTION
5V POWER SUPPLY
AMI OR HDB3 CODE SELECTION
PARALLEL OR SERIAL MICROPROCESSOR
INTERFACE OPTION
BOTH µp AND STAND ALONE MODE AVAIL-
ABLE
DESCRIPTION
STLC5432, CMOS device, interfaces the multi-
plex system to the physical CEPT Transmission
link at 2048Kb/s. Furthermore, thanks to its flexi-
bility, it is the optimum solution also for the ISDN
application as PRIMARY RATE CONTROLLER.
The receive circuit performances exceed CCITT
recommendation and the line driver outputs meet
the G.703 specifications.
STLC5432 is the real single chip solution that al-
lows the best system flexibility and easy design.
STLC5432 can work either in 2048 or 4096 or
8192 Kbit/s systems programming the CR4 regis-
ter (when parallel micro interface selected).
TQFP44 (10 x 10)
ORDERING NUMBER: STLC5432Q
PIN CONNECTION (Top view)
GNDD
SA/RESET
DIN
A/D0
A/D1
A/D2
A/D3
INT
RCLI
BRDI
DOUT
44 43 42 41 40 39 38 37 36 35 34
1 33
2 32
3 31
4 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
BXDI
AL0
AL1
A/D7
A/D6
A/D5
A/D4
R/W/WR
LFSX
LFSR
LCLK
D93TL043D
July 1996
1/46
1 page  
STLC5432
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC to GND
VI
ILO1, IOL2
IC
Tstg
TL
Parameter
Supply Voltage to Ground
Voltage at any digital or analog input
Current at LO1 and LO2
Current at any digital or analog input
Storage temperature range
Lead Temperature (soldering, 10s)
Value
7
VCC+1 to GND-1
±100
±30
-65 to +150
+300
Unit
V
V
mA
mA
°C
°C
THERMAL DATA
Symbol
Rth j-amb
Parameter
Thermal Resistance Junction to ambient
Max.
Value
50
Unit
°C/W
ELECTRICAL CHARACTERISTICS (VCC = 5V ±5%, Tamb = 0 to 70°C; Typical characteristics are speci-
fied at VCC = 5V, Tamb = 25°C; all signal are referenced to GND, unless otherwise specified.)
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
DIGITAL INTERFACE
Vil Input Low Voltage
All digital inputs
0.8 V
Vih Input High Voltage
All digital inputs
2.2
V
Vilx Input Low Voltage
XTAL1 input
0.5 V
Vihx
Input High Voltage
Vol Output Low Voltage
Voh Output High Voltage
Iil Input Low Current
Iih Input High Current
Ioz Output Current in High
Impedance (tri-state)
XTAL1 input
IL = 7mA for pins AL0, AL1,
INT, DOUT, HCR, LCR.
All other digital outputs:
IL = 1mA
VCC-0.5
IL = 7mA for pins AL0, AL1,
INT, DOUT, HCR, LCR.
All other digital outputs:
IL = 1mA
Any digital input, Gnd < Vin < Vil
2.4
2.4
Any digital input, Gnd < Vin <
VCC
All digital tri-state I/Os without
internal pull-up or pull-down
resistor.
V
0.4 V
0.4 V
V
V
10 µA
10 µA
10 µA
LINE INTERFACE FEATURES
Zin Differential Input Resistance
DC measurement between LI1
and LI2 with the equalizer not
connected
200
KΩ
Vin Rx sensitivity
Relative to LI1/LI2 pins with
fixed detection threshold
0.6
Vpk
Vpk75
Vpk120
Sym
Transmit amplitude
Transmit Amplitude
Pulses Symetry
75Ω at transformer secondary 2.14 2.37 2.60 Vpk
120Ω at transformer secondary 2.7
3 3.30 Vpk
75Ω or 120Ω at transformer
secondary
5%
Zero
Zero level
% nominal amplitude
10 %
Pwdth
Zout
Tx pulses width
Differential Output Resistance
at 50% of peak amplitude
219 244 269
1
ns
Ω
MASTERCLOCK
MCLK MCLK Frequency
32.764
MHz
MCLK Frequency tolerance
–50 50 ppm
JITTER PERFORMANCES (for jitter transfer function and admissible jitter please report to the corresponding
characteristics plotted in following page).
Intrinsic jitter
Filter 20Hz - 100KHz
0.125 UI
Intrinsic jitter
Filter 700Hz - 100KHz
0.12 UI
5/46
5 Page 
STLC5432
5.3.1 Typical case
Remote entity transmits Frame Alignment Signal
(FAS) and Multiframe Alignment Signal (MFAS).
As soon as lost of Frame Alignment is occured
(LOF = 1), the local receiver recovers FAS from
254 up to 500µs after. As soon as FAS is recov-
ered (LOF = 0), the local receiver recovers MFAS
from 4 up to 6ms after.
5.3.2 Old Existing Equipment Case
Remote entity transmits Frame Alignment Signal
(FAS) without Multiframe Alignment Signal (MFAS).
As soon as lost of Frame Alignment is occured
(LOF=1), the local receiver recovers FAS from 254
up to 500µs after. Then LOF = 0, and 400ms after
the local receiver indicates that the Multiframe Aligne-
ment Signal has not been recovered (MFNR = 1).
5.3.3 Particular Case: Spurious Frame Alignment
Signal
Local receiver receives true FAS and true MFAS
among several spurious FAS.
Multiframe Alignment signal (MFR=1) is recovered
from 8 to 400ms after the Frame Alignment signal
is recovered (LOF=0). Then, this FAS is either a
spurious one (the ”Spurious Time slot Zero” is car-
rying FAS without MFAS), or true FAS.
Anyway, when the Multiframe Alignment has been
recovered (MFR=1), the good Frame Alignment
Signal is taken into account and data are loaded
into the Frame Memory at the good location.
See Fig. 13 synchronization algorithm.
5.3.4 Worst Case
Local receiver receives true FAS and true MFAS
among several spurious FAS and several spuri-
ous MFAS.
In this case, if the circuit has recovered a spuri-
ous FAS and MFAS, the CRC blocks will be de-
tected with an high error rate. As soon as 915 er-
rored CRC block within 1000 will be detcted, the
MFAS will be assumed as spurious and a new re-
search starts at the point just after the location of
the assumed spurious Frame Alignement Signal.
5.4 Transmitter SIDE
The Frame Alignement Signal is transmitted con-
tinuously on the transmitter side, with bit 1 of TS0
at logical 1. The MFAS signal is transmitted in ac-
cordance with NMF bit register (CR5 Register): if
NMF is programmed to ”1” Logic, no MFAS is
transmitted; if NMF is programmed to ”0” Logic
the MFAS signal is transmitted continuously.
Table 2.
LOF
1
0
0
0
MFR
0
0
1
0
MFNR
RECEIVER STATE
0 FAS or MFAS has been lost.
State: Research of FAS
0 FAS has been recovered.
State: Research of MFAS
0 Frame and Multiframe recovered
State: Good working.
1 Frame recovered.
State: Good working without
multiframe received from
transmitting side.
6 Interfacing with the microprocessor
The device can work in one of the 3 following
modes :
– Parallel microprocessor Interface Mode
– Serial microprocessor Interface Mode
– Without microprocessor : Stand Alone Mode.
The choice is done by means of the SA/Reset, P0
and P1 pins.
6.1 Parallel Microprocessor Interface Mode
The microprocessor can read (or write) the regis-
ters of the STLC5432 using the fifteen parallel In-
terface pins.
The use of TSO (Time Slot Zero) of DIN and
DOUT digital multiplex is defined by TSOE bit of
CR5 Register.
– If TSOE = 1, TSO on DIN multiplex Input is
used to transfer Sa4 to Sa8 bits to the line
and TSO on DOUT multiplex output is used to
transfer Sa4 to Sa8 bits from the line.
– If TSOE = 0, DOUT output is high impedance
during TSO, and DIN Input ignores data dur-
ing TSO.
6.2 Serial Microprocessor Interface Mode
Fifteen parallel Interface pins are ignored, they
are tied to ground. In this mode, the time slots 0
of internal multiplexes are considered like a chan-
nel used by the devices and the control entity lo-
cated in the system to communicate. This chan-
nel can be switched across a switching network
-or not- before its final destination.
The message is constituted by two bytes which
are transmitted on two consecutive Time Slots
Zero.
The bits of word are numbered 0 to 7, bit 0 is
transmitted first. When the bit 7 of a byte is 0, this
byte is the first word of the message.
The bit 6, of the first word, is R/W bit:
R/W = 1. Message to read a register whose ad-
dress is designated by the following bits of the
word ( A 0/5).
11/46
11 Page | ||
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| PDF Descargar | [ Datasheet STLC5432.PDF ] | |
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