PDF STLC5464 Data sheet ( Hoja de datos )

Número de pieza	STLC5464
Descripción	MULTI-HDLCWITH n x 64 SWITCHING MATRIX ASSOCIATED
Fabricantes	ST Microelectronics
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No Preview Available ! STLC5464 MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED . 32 TxHDLCs WITH BROADCASTING CAPA- BILITY AND/OR CSMA/CR FUNCTION WITH AUTOMATIC RESTART IN CASE OF TX . FRAME ABORT 32 RxHDLCs INCLUDING ADDRESS REC- . OGNITION 16 COMMAND/INDICATE CHANNELS (4 OR . 6-BIT PRIMITIVE) 16 MONITOR CHANNELS PROCESSED IN . ACCORDANCE WITH GCI OR V* 256 x 256 SWITCHING MATRIX WITHOUT BLOCKING AND WITH TIME SLOT SE- QUENCE INTEGRITY AND LOOPBACK PER . BIDIRECTIONAL CONNECTION DMA CONTROLLER FOR 32 Tx CHANNELS . AND 32 Rx CHANNELS HDLCs AND DMA CONTROLLER ARE CAPA- BLE OF HANDLING A MIX OF LAPD, LAPB, . SS7, CAS AND PROPRIETARY SIGNALLINGS EXTERNAL SHARED MEMORY ACCESS BE- TWEEN DMA CONTROLLER AND MICRO- . PROCESSOR SINGLE MEMORY SHARED BETWEEN n x MULTI-HDLCs AND SINGLE MICRO- PROCESSOR ALLOWS TO HANDLE n x 32 CHANNELS . BUS ARBITRATION . INTERFACE FOR VARIOUS 8,16 OR 32 BIT . MICROPROCESSORS RAM CONTROLLER ALLOWS TO INTER- FACE UP TO : -16 MEGABYTES OF DYNAMIC RAM OR . -1 MEGABYTE OF STATIC RAM INTERRUPT CONTROLLER TO STORE AUTOMATICALLY EVENTS IN SHARED . MEMORY PQFP160 PACKAGE DESCRIPTION The STLC5464 is a Subscriber line interface card controller for Central Office, Central Exchange, NT2 and PBX capable of handling : - 16 U Interfaces or - 2 Megabits line interface cards or - 16 SLICs (Plain Old Telephone Service) or - Mixed analogue and digital Interfaces (SLICs or U Interfaces) or - 16 S Interfaces - Switching Network with centralized processing PQFP160 (Plastic Quad Flat Pack) ORDER CODE : STLC5464 May 1997 1/83 1 page STLC5464 CONTENTS (continued) Page IX IX.1 IX.2 IX.2.1 IX.2.2 IX.2.3 IX.3 IX.3.1 IX.3.2 IX.3.3 IX.4 IX.5 IX.5.1 IX.5.2 IX.6 IX.6.1 IX.6.2 EXTERNAL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NITIALIZATION BLOCK IN EXTERNAL MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVE DESCRIPTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bits written by the Microprocessor only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bits written by the Rx DMAC only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSMIT DESCRIPTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bits written by the Microprocessor only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bits written by the Rx DMAC only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVE & TRANSMIT HDLC FRAME INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVE COMMAND / INDICATE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Command / Indicate Interrupt when TSV = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Command / Indicate Interrupt when TSV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVE MONITOR INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Monitor Interrupt when TSV = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Monitor Interrupt when TSV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 75 76 76 76 76 77 77 78 78 78 79 79 80 80 80 81 X PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5/83 5 Page STLC5464 I - PIN INFORMATION (continued) I.2 - Pin Description (continued) Pin N° Symbol Type Function MICROPROCESSOR INTERFACE (continued) 51 NLDS I3 Lower Data Strobe (68000) 52 NUDS I3 Bus High Enable (Intel) / Upper Data Strobe (68000) 53 NDTACK O8D Data Transfer Acknowledge (68000) 54 READY O8T Data Transfer Acknowledge (Intel) 55 NAS/ALE I3 Address Strobe(Motorola) / Addresss Latch Enable(Intel) 56 R/W / NWR I3 Read/Write (Motorola) / Write(Intel) 57 NDS/NRD I3 Data Strobe (Motorola) /Read Data (Intel) 63 A0/AD0 I/O Address bit 0 (Motorola) / Address/Data bit 0 (Intel) 64 A1/AD1 I/O Address bit 1 (Motorola) / Address/Data bit 1 (Intel) 65 A2/AD2 I/O Address bit 2 (Motorola) / Address/Data bit 2 (Intel) 66 A3/AD3 I/O Address bit 3 (Motorola) / Address/Data bit 3 (Intel) 67 A4/AD4 I/O Address bit 4 (Motorola) / Address/Data bit 4 (Intel) 68 A5/AD5 I/O Address bit 5 (Motorola) / Address/Data bit 5 (Intel) 69 A6/AD6 I/O Address bit 6 (Motorola) / Address/Data bit 6 (Intel) 70 A7/AD7 I/O Address bit 7 (Motorola) / Address/Data bit 7 (Intel) 71 A8/AD8 I/O Address bit 8 (Motorola) / Address/Data bit 8 (Intel) 72 A9/AD9 I/O Address bit 9 (Motorola) / Address/Data bit 9 (Intel) 75 A10/AD10 I/O Address bit 10 (Motorola) / Address/Data bit 10 (Intel) 76 A11/AD11 I/O Address bit 11 (Motorola) / Address/Data bit 11 (Intel) 77 A12/AD12 I/O Address bit 12 (Motorola) / Address/Data bit 12 (Intel) 78 A13/AD13 I/O Address bit 13 (Motorola) / Address/Data bit 13 (Intel) 79 A14/AD14 I/O Address bit14 (Motorola) / Address/Data bit 14 (Intel) 80 A15/AD15 I/O Address bit15 (Motorola) / Address/Data bit 15 (Intel) 81 A16 I1 Address bit16 (Motorola) / Address bit 16 (Intel) 82 A17 I1 Address bit17 (Motorola) / Address bit 17 (Intel) 83 A18 I1 Address bit18 (Motorola) / Address bit 18 (Intel) 84 A19 I1 Address bit19 (Motorola) / Address bit 19 (Intel) 85 A20/ADM15 I/O Address bit 20 from µP (input) / Address bit 15 for SRAM (output) 86 A21/ADM16 I/O Address bit 21 from µP (input) / Address bit 16 for SRAM (output) 87 A22/ADM17 I/O Address bit 22 from µP (input) / Address bit 17 for SRAM (output) 88 A23/ADM18 I/O Address bit 23 from µP (input) / Address bit 18 for SRAM (output) 91 DO I/O Data bit 0 for µP if not multiplexed (see Note 1). 92 D1 I/O Data bit 1 for µP if not multiplexed 93 D2 I/O Data bit 2 for µP if not multiplexed 94 D3 I/O Data bit 3 for µP if not multiplexed 95 D4 I/O Data bit 4 for µP if not multiplexed 96 D5 I/O Data bit 5 for µP if not multiplexed 97 D6 I/O Data bit 6 for µP if not multiplexed 98 D7 I/O Data bit 7 for µP if not multiplexed 99 D8 I/O Data bit 8 for µP if not multiplexed Type : I1 = Input TTL ; I2 = I1 + Pull-up ; O4 = Output CMOS 4mA ; O4T = O4 + Tristate ; O8D = Output CMOS 8mA, Open Drain ; O8T = Output CMOS 8mA, Tristate I3 = I1 + Hysteresis ; I4 = I3 + Pull-up ; O8 = Output CMOS 8mA, ”1” and ”0” at Low Impedance ; O8DT = Output CMOS 8mA, Open Drain or Tristate ; 11/83 11 Page

Páginas	Total 30 Páginas
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