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Número de pieza | DS1007 | |
Descripción | 7-1 Silicon Delay Line | |
Fabricantes | Dallas Semiconducotr | |
Logotipo | ||
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DS1007
7-1 Silicon Delay Line
FEATURES
All-silicon time delay
7 independent buffered delays
Delay tolerance ±2 ns
Four delays can be custom set between 3 ns
and 10 ns
Three delays can be custom set between 9 ns
and 40 ns
Delays are stable and precise
Economical
Auto-insertable, low profile
Surface mount 16-pin SOIC
Low-power CMOS
TTL/CMOS-compatible
Vapor phase, IR and wave solderable
Custom specifications available
Quick turn prototypes
PIN ASSIGNMENT
IN1 1
16 IN3
OUT1 2
15 OUT3
IN2 3
14 IN4
OUT2 4
13 OUT4
VCC 5
IN5 6
12 GND
11 OUT7
OUT5
IN6
7
8
10 IN7
9 OUT6
DS1007 16-Pin DIP (300-mil)
See Mech. Drawings Section
IN1
OUT1
IN2
OUT2
VCC
IN5
OUT5
IN6
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
IN3
OUT3
IN4
OUT4
GND
OUT7
IN7
OUT6
DS1007S 16-Pin SOIC
(300-mil)
See Mech. Drawings Section
PIN DESCRIPTION
IN1 - IN7 - Inputs
Out1 – Out7 - Outputs
GND
- Ground
VCC - +5 Volts
DESCRIPTION
The DS1007 7-in-1 Silicon Delay Line provides seven independent delay times which are set by Dallas
Semiconductor to the customer’s specification. The delay times can be set from 3 ns to 40 ns with an
accuracy of ±2 ns at room temperature. The device is offered in both a 16-pin DIP and a 16-pin SOIC.
Since the DS1007 is an all-silicon solution, better economy and reliability are achieved when compared to
older methods using hybrid technology. The DS1007 reproduces the input logic state at the output after
the fixed delay. Dallas Semiconductor can customize standard products to meet special needs. For special
requests and rapid delivery, call (972) 371–4348.
1 of 6
111799
1 page NOTES:
1. All voltages are referenced to ground.
DS1007
2. Measured with outputs open.
3. VCC = 5V @25°C. Delays accurate on rising edges within ±2 ns.
4. See Test Conditions below.
5. All output delays in the same speed output tend to vary unidirectionally with temperature or voltage
range (i.e., if Out 2 slows down, all other outputs also slow down).
6. Period specifications may be exceeded; however, accuracy will be application-sensitive (decoupling,
layout, etc.).
7. tPU = 0 ms for Out 1 through Out 4.
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of the corresponding output pulse.
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1007.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected between the input and each output. Each
output is selected and connected to the counter by a VHF switch control unit. All measurements are fully
automated, with each instrument controlled by a central computer over an IEEE 488 bus.
5 of 6
5 Page |
Páginas | Total 6 Páginas | |
PDF Descargar | [ Datasheet DS1007.PDF ] |
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