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PDF DS005 Data sheet ( Hoja de datos )
| Número de pieza | DS005 | |
| Descripción | XC4000XL Electrical Specifications | |
| Fabricantes | Xilinx | |
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R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL Electrical Specifications
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance:
Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or
devicefamilies. Values are subject to change. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked:
Specifications not identified as either Advance or Preliminary are to be considered Final.
Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions.
All specifications subject to change without notice.
XC4000XL D.C. Characteristics
Absolute Maximum Ratings
Description
VCC
VIN
VTS
VCCt
TSTG
TSOL
TJ
Supply voltage relative to Ground
Input voltage relative to Ground (Note 1)
Voltage applied to 3-state output (Note 1)
Longest Supply Voltage Rise Time from 1 V to 3V
Storage temperature (ambient)
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
Junction Temperature
Ceramic packages
Plastic packages
-0.5 to 4.0
-0.5 to 5.5
-0.5 to 5.5
50
-65 to +150
+260
+150
+125
Note 1: Maximum DC excursion above Vcc or below Ground must be limited to either 0.5 V or 10 mA, whichever is easier to
achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot toVCC +2.0 V, provided this over or
undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.
Units
V
V
V
ms
°C
°C
°C
°C
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
Recommended Operating Conditions
Symbol
Description
Min Max
VCC
VIH
VIL
TIN
Notes:
Supply voltage relative to Gnd, TJ = 0 °C to +85°C
Supply voltage relative to Gnd, TJ = -40°C to +100°C
High-level input voltage
Commercial
Industrial
Low-level input voltage
Input signal transition time
3.0
3.0
50% of VCC
0
3.6
3.6
5.5
30% of VCC
250
At junction temperatures above those listed above, all delay parameters increase by 0.35% per °C.
Input and output measurement threshold is ~50% of VCC.
Units
V
V
V
V
ns
6
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-73
1 page  
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL CLB Characteristics
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
CLB Switching Characteristic Guidelines
Speed Grade
Description
Symbol
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H’ to X/Y outputs
F/G inputs via transparent latch to Q outputs
C inputs via SR/H0 via H to X/Y outputs
C inputs via H1 via H to X/Y outputs
C inputs via DIN/H2 via H to X/Y outputs
C inputs via EC, DIN/H2 to YQ, XQ output (bypass)
CLB Fast Carry Logic
TILO
TIHO
TITO
THH0O
THH1O
THH2O
TCBYP
Operand inputs (F1, F2, G1, G4) to COUT
Add/Subtract input (F3) to COUT
Initialization inputs (F1, F3) to COUT
CIN through function generators to X/Y outputs
CIN to COUT, bypass function generators
Carry Net Delay, COUT to CIN
Sequential Delays
TOPCY
TASCY
TINCY
TSUM
TBYP
TNET
Clock K to Flip-Flop outputs Q
Clock K to Latch outputs Q
Setup Time before Clock K
TCKO
TCKLO
F/G inputs
F/G inputs via H
C inputs via H0 through H
C inputs via H1 through H
C inputs via H2 through H
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
CIN input via F/G
CIN input via F/G and H
Hold Time after Clock K
TICK
TIHCK
THH0CK
THH1CK
THH2CK
TDICK
TECCK
TRCK
TCCK
TCHCK
F/G inputs
F/G inputs via H
C inputs via SR/H0 through H
C inputs via H1 through H
C inputs via DIN/H2 through H
C inputs via DIN/H2
C inputs via EC
C inputs via SR, going Low (inactive)
Clock
TCKI
TCKIH
TCKHH0
TCKHH1
TCKHH2
TCKDI
TCKEC
TCKR
Clock High time
Clock Low time
Set/Reset Direct
TCH
TCL
Width (High)
Delay from C inputs via S/R, going High to Q
Global Set/Reset
TRPW
TRIO
Minimum GSR Pulse Width
Delay from GSR input to any Q
Toggle Frequency (MHz) (for export control)
TMRW
TMRQ
FTOG (MHz)
-3 -2 -1 -09
Min Max Min Max Min Max Min Max
1.6 1.5 1.3 1.2
2.7 2.4 2.2 2.0
2.9 2.6 2.2 2.0
2.5 2.2 2.0 1.8
2.4 2.1 1.9 1.6
2.5 2.2 2.0 1.8
1.5 1.3 1.1 1.0
2.7 2.3 2.0 1.6
3.3 2.9 2.5 1.8
2.0 1.8 1.5 1.0
2.8 2.6 2.4 1.7
0.26 0.23 0.20 0.14
0.32 0.28 0.25 0.24
2.1 1.9 1.6 1.5
2.1 1.9 1.6 1.5
1.1 1.0 0.9 0.8
2.2 1.9 1.7 1.6
2.0 1.7 1.6 1.4
1.9 1.6 1.4 1.2
2.0 1.7 1.6 1.4
0.9 0.8 0.7 0.6
1.0 0.9 0.8 0.7
0.6 0.5 0.5 0.4
2.3 2.1 1.9 1.3
3.4 3.0 2.7 2.1
0000
0000
0000
0000
0000
0000
0000
0000
3.0 2.8 2.5 2.3
3.0 2.8 2.5 2.3
3.0 2.8 2.5 2.3
3.7 3.2 2.8 2.7
19.8 17.3 15.0 14.0
See Table on page 85 for TRRI values per device.
166 179 200 217
-08
Min Max
1.1
1.9
1.8
1.8
1.5
1.8
0.9
1.6
1.8
0.9
1.5
0.14
0.24
1.4
1.4
0.8
1.5
1.4
1.1
1.4
0.6
0.7
0.4
1.2
2.0
0
0
0
0
0
0
0
0
2.1
2.1
2.3
2.6
14.0
238
6
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-77
5 Page 
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Global Early Clock BUFGEs 1, 2, 5, and 6 Set-up and Hold for IFF and FCL
Description
Speed Grade -3 -2 -1 -09 -08
Units
Symbol
Device Min Min Min Min Min
Input Setup and Hold
Times
No Delay
XC4002XL 2.8 / 1.5 2.5 / 1.3 2.2 / 1.2 1.9 / 1.0
ns
Global Early Clock and IFF TPSEN/TPHEN XC4005XL
Global Early Clock and
TPFSEN/TPFHEN XC4010XL
FCL XC4013XL
1.2 / 4.1 1.1 / 3.6 0.9 / 3.1 0.8 / 2.7
1.2 / 4.4 1.1 / 3.8 0.9 / 3.3 0.8 / 2.9
1.2 / 4.7 1.1 / 4.1 0.9 / 3.6 0.8 / 3.1 0.5 / 2.7
ns
ns
ns
XC4020XL 1.2 / 4.6 1.1 / 4.0 0.9 / 3.5 0.8 / 3.0
ns
XC4028XL 1.2 / 5.3 1.1 / 4.6 0.9 / 4.0 0.8 / 3.5
ns
XC4036XL 1.2 / 6.7 1.1 / 5.8 0.9 / 5.1 0.8 / 4.4 0.5 / 3.7 ns
XC4044XL 1.2 / 6.5 1.1 / 5.7 0.9 / 4.9 0.8 / 4.3
ns
XC4052XL 1.2 / 6.7 1.1 / 5.8 0.9 / 5.1 0.8 / 4.4
ns
XC4062XL 1.2 / 8.4 1.1 / 7.3 0.9 / 6.3 0.8 / 5.5 0.5 / 4.7 ns
XC4085XL 1.2 / 8.7 1.1 / 7.5 0.9 / 6.6 0.8 / 5.7
ns
Partial Delay
XC4002XL 8.1 / 0.9 7.0 / 0.8 6.1 / 0.7 5.3 / 0.6
ns
Global Early Clock and IFF TPSEP/TPHEP XC4005XL 9.0 / 0.0 8.5 / 0.0 8.0 / 0.0 7.5 / 0.0
Global Early Clock and
TPFSEP/TPFHEP XC4010XL 11.9 / 0.0 10.4 / 0.0 9.0 / 0.0 8.0 / 0.0
FCL XC4013XL* 6.4 / 0.0 5.9 / 0.0 5.4 / 0.0 4.9 / 0.0 4.4 / 0.0
ns
ns
ns
XC4020XL 10.8 / 0.0 10.3 / 0.0 9.8 / 0.0 9.0 / 0.0
ns
XC4028XL 14.0 / 0.0 12.2 / 0.0 10.6 / 0.0 9.8 / 0.0
ns
XC4036XL* 7.0 / 0.0 6.6 / 0.0 6.2 / 0.0 5.2 / 0.0 4.7 / 0.0 ns
XC4044XL 14.6 / 0.0 12.7 / 0.0 11.0 / 0.0 10.8 / 0.0
ns
XC4052XL 16.4 / 0.0 14.3 / 0.0 12.4 / 0.0 11.4 / 0.0
ns
XC4062XL* 9.0 / 0.8 8.6 / 0.8 8.2 / 0.8 7.0 / 0.8 6.3 / 0.5 ns
XC4085XL 16.7 / 0.0 14.5 / 0.0 12.6 / 0.0 11.6 / 0.0
ns
Full Delay
XC4002XL 6.7 / 0.0 5.8 / 0.0 5.1 / 0.0 4.4 / 0.0
ns
Global Early Clock and IFF TPSED/TPHED
XC4005XL 10.8 / 0.0 9.4 / 0.0 8.2 / 0.0 7.1 / 0.0
XC4010XL 10.3 / 0.0 9.0 / 0.0 7.8 / 0.0 6.8 / 0.0
ns
ns
XC4013XL* 10.0 / 0.0 8.7 / 0.0 7.6 / 0.0 6.6 / 0.0 6.0 / 0.0 ns
XC4020XL 12.0 / 0.0 10.4 / 0.0 9.1 / 0.0 7.9 / 0.0
ns
XC4028XL 12.6 / 0.0 11.0 / 0.0 9.5 / 0.0 8.3 / 0.0
ns
XC4036XL* 12.2 / 0.0 10.6 / 0.0 9.2 / 0.0 8.0 / 0.0 7.2 / 0.0 ns
XC4044XL 13.8 / 0.0 12.0 / 0.0 10.5 / 0.0 9.1 / 0.0
ns
XC4052XL 14.1 / 0.0 12.3 / 0.0 10.7 / 0.0 9.3 / 0.0
ns
XC4062XL* 13.1 / 0.0 11.4 / 0.0 9.9 / 0.0 8.6 / 0.0 7.8 / 0.0 ns
XC4085XL 17.9 / 0.0 15.6 / 0.0 13.6 / 0.0 11.8 / 0.0
ns
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
* The XC4013XL, XC4036XL, and 4062XL have significantly faster partial and full delay setup times than other devices.
Notes: Input setup time is measured with the fastest route and the lightest load.
Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification.
6
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-83
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet DS005.PDF ] | |
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