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PDF STA400A Data sheet ( Hoja de datos )
| Número de pieza | STA400A | |
| Descripción | XMRADIO SDARS CHANNEL DECODER | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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STA400A
XMRADIO® SDARS CHANNEL DECODER
FRONT END INTERFACE
s TWO INTERNAL 10 BIT A/D CONVERTERS
s TWO QPSK DEMODULATORS FOR
SATELLITE BRANCH
s ONE MULTICARRIER DEMODULATOR FOR
TERRESTRIAL BRANCH
s SATELLITE SYMBOL FREQUENCY: 1.64
MBAUD
s TERRESTRIAL SYMBOL FREQUENCY: 2.99
MBAUD
s DIGITAL ROOT RAISED COSINE NYQUIST
FILTER: 15% ROLL-OFF
s FFT LENGTH: 768 SUB-CARRIERS
s FULL DIGITAL CARRIER AND FREQUENCY
RECOVERY AND TRACKING LOOPS
s FREQUENCY INVERSION COMPENSATION
FOR HIGH-SIDE/LOW-SIDE MIXER
INJECTION
s LOCK DETECTORS, C/N INDICATOR, ON
CHIP BER ESTIMATORS
s TWO DIGITAL AGCs: INTERNAL SIGNAL
POWER ESTIMATION AND FILTERING
s 1 BIT PDM AGCs CONTROL SIGNAL
OUTPUTS
TDM DECODING AND MANAGEMENT
s SATELLITE AND TERRESTRIAL FRAME
SYNCHRONIZATION
s SATELLITE PHASE AMBIGUITY RESOLUTION
s TDM DEMULTIPLEXING
s PRIME RATE CHANNEL (PRC)
DEMULTIPLEXING
s EXTERNAL MEMORY CONTROLLING
FORWARD ERROR CORRECTION
s VITERBI DECODER: K=7, R=1/3
s SATELLITE DEPUNCTURING: RATE 3/4
s TERRESTRIAL DEPUNCTURING: RATE 3/5
s CONVOLUTIONAL TIME DEINTERLEAVER
OVER 4.7 SEC
s BLOCK DEINTERLEAVER OVER 2 RS
BLOCKS
s REED-SOLOMON DECODER: (255,223). UP
TO 16 BYTES CORRECTION CAPABILITY.
September 2003
TQFP144
ORDERING NUMBER: STA400A
T H I S D E V I C E C A N B E S O L D O N LY TO
CUSTOMERS THAT HAVE SIGNED A LICENSE
AGREEMENT WITH XM SATELLITE RADIO.
s ENERGY DISPERSAL DESCRAMBLER
s SAT-SAT AND TERR-SAT DIVERSITY
COMBINING
BACK END INTERFACE
s TWO PAYLOAD CHANNEL BITSTREAM
INTERFACES
s PAYLOAD CHANNEL SELECTION LOGIC
s DESIGNED TO WORK WITH THE STA450A
SERVICE AND SOURCE DECODER
LOW POWER TECHNOLOGY
s 1.8V, 0.18µm TECHNOLOGY
s 3.3V CAPABLE I/Os
CONTROL
s IIC-BUS SLAVE CONTROL INTERFACE
s DEVICE ADDRESS: 1101010
DESCRIPTION
The SDARS is a satellite transmission system based
on two geostationary satellites on the East and West
coasts of the Continental United States (CONUS). In
the urban areas, where the line of sight reception of
the satellites is difficult or not possible, the service is
covered by terrestrial repeaters adopting a MultiCar-
rier Modulation scheme.
Designed for digital radio receivers compatible with
the XMRadio SDARS System, the STA400A Chan-
nel Decoder integrates all the functions to demodu-
1/117
1 page  
STA400A
PIN DESCRIPTION (Continued)
Pin N°
35
36
37
38
[42:51]
Pin Name
MCLKO
MCLKON
LOCK_S1
LOCK_S2
IF2TD[9:0]
52
53
56
57
[58:65]
FTESTEN
INTR
CLKD
LOCK_M
IF2SD[7:0]
69 SCL
70 SDA
71 TEST_EN
72 SCAN_EN
73 BIST_EN
74 PCTS_EF2
75 PCFS2
76 PCSD2
77 PCDC2
78 PCBS2
79 PCTS_EF1
82 PCFS1
83 PCSD1
85 PCDC1
86 PCBS1
87 MAO1
88 MAO2
89,93,94 NC
92 MAI1
Type
O
O
O
O
I
Function
Master Clock Output
Inverted Master Clock Output
Satellite Dem1 Lock Indicator
Satellite Dem2 Lock Indicator
Terr. 2nd IF Digital Input
I Functional Test Enable (1=enable)
O Interrupt
O Divided Master Clock
O Terrestrial Demodulator Lock Indicator
I Sat. 2nd IF Digital Input
I IIC-bus Serial Clock
I/O IIC-bus Serial Data
I ATPG Test Enable (1=Enabled)
I Scan Enable (1=Enabled)
I RAM Bilt In Self Test Enable (1=Enabled)
O Payload Channel TSCC Sync2/ErrorFlag 2
(432 msec)
O Payload Channel PRC Frame Sync 2
O Payload Channel Serial Data 2
O Payload Channel Data Clock 2
O Payload Channel Byte Sync2 (RS Symbol)
O Payload Channel TSCC Sync1/ ErrorFlag1
(432 msec)
O Payload Channel PRC Frame Sync1
O Payload Channel Serial Data 1
O Payload Channel Data Clock 1
O Payload Channel Byte Sync1 (RS Symbol)
O Mobile Adapter Output #1
O Mobile Adapter Output #2
Not Connected.
I Mobile Adapter Input
PAD Description
4mA Output Driver
4mA Output Driver
2mA Output Driver
2mA Output Driver
Input Pad Buffer. High
Drive.
Buffer with Pull-Down
2mA Output Driver
2mA Output Driver
2mA Output Driver
Input Pad Buffer. High
Drive
Schmitt Trigger Buffer
Schmitt Trigger BiDir
Buffer. 4mA Driver
Buffer with Pull-Down
Buffer with Pull-Down
Buffer with Pull-Down
2mA Output Driver
2mA Output Driver
2mA Output Driver
2mA Output Driver
2mA Output Driver
2mA Output Driver
2mA Output Driver
2mA Output Driver
2mA Output Driver
2mA Output Driver
2mA Output Driver
2mA Output Driver
Buffer with Pull-Down
5/117
5 Page 
STA400A
two embedded ADCs. This functionality gives the possibility to use two external ADCs connected to the satellite
digital input (IF2SD[7:0]) and to the terrestrial digital input (IF2TD[9:0]) respectively. The digital inputs must be
tied to ground when not used.
The FTESTOUT[15:0] pins are available for testing purpose and for measuring system performance.
1.1 IF SAMPLING AND CONTROL INTERFACE
This block comprises the embedded ADCs, the satellite and terrestrial AGCs and CDEC CONTROL registers.
It receives from the RF Front-End the two QPSK modulated satellite signals centered at 6.095 MHz and the Mul-
tiCarrier Modulated terrestrial signal centered at 2.99 MHz (2nd IF frequencies). These signals are over sampled
by the 23.92 MHz master clock (MCLK) and converted to digital on 8 bits for the satellite composite signal and
on 10 bits for the terrestrial signal (see fig.1).
The programmable registers of the IF Sampling block are described in section 2.6.
Embedded ADCs
The two embedded ADCs are 10 bit high speed A/D converters designed for high sampling rate (up to 50 MHz)
and low power consumption (1mW/MHz) with a full differential pipeline conversion architecture that needs 6
clock periods for one conversion.
A voltage reference is integrated in the circuit for external components minimization but it is possible to use an
external reference.
The ADCs provide also a reduced input capacitance, a low reference capability and a wide input bandwidth
(50MHz).
Pins IF2xA_P IF2xA_N can be connected as full-differential inputs or as pseudo-differential input. In fig.4 the
latter configuration is showed (x=S for Satellite and x=T for Terrestrial branch).
Figure 4. ADC Pseudo-Differental Configuration
2.2uF
100nF
47K
50ohm
50ohm
33ohm
VIN
xADCREF
xINCM
IF2xA_P
47pF
27pF
DATA[9:0]
33ohm
IF2xA_N
xVCMO
xREFP
xREFM
100pF
100nF 100pF
100nF
FROM
INTERNAL CLK
DISTRIBUTION
The two pins xREFM (Bottom of the reference ladder) and xREFP (Top of the reference ladder) are decoupling
nodes for conversion dynamic adjustment; when the internal reference is used these pins must be connected
as showed in figure 4. Pin xADCREF is connected with an external resistor (typical value 47 Kohm) to trim the
internal bias current, xINCM is the output common mode used to centre the external input network and xVCMO
is the internal common mode that can be externally filtered by a capacitor.
11/117
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STA400A.PDF ] | |
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