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What is OR2C06A?

This electronic component, produced by the manufacturer "Lattice", performs the same function as "Field-Programmable Gate Ayyays".


OR2C06A Datasheet PDF - Lattice

Part Number OR2C06A
Description Field-Programmable Gate Ayyays
Manufacturers Lattice 
Logo Lattice Logo 


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Data Sheet
January 2002
ORCA® Series 2
Field-Programmable Gate Arrays
Features
High-performance, cost-effective, low-power
0.35 µm CMOS technology (OR2CxxA), 0.3 µm CMOS
technology (OR2TxxA), and 0.25 µm CMOS technology
(OR2TxxB), (four-input look-up table (LUT) delay less
than 1.0 ns with -8 speed grade)
High density (up to 43,200 usable, logic-only gates; or
99,400 gates including RAM)
Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are
5 V tolerant to allow interconnection to both 3.3 V and
5 V devices, selectable on a per-pin basis)
Four 16-bit look-up tables and four latches/ip-ops per
PFU, nibble-oriented for implementing 4-, 8-, 16-, and/or
32-bit (or wider) bus structures
Eight 3-state buffers per PFU for on-chip bus structures
Fast, on-chip user SRAM has features to simplify RAM
design and increase RAM speed:
— Asynchronous single port: 64 bits/PFU
— Synchronous single port: 64 bits/PFU
— Synchronous dual port: 32 bits/PFU
Improved ability to combine PFUs to create larger RAM
structures using write-port enable and 3-state buffers
Fast, dense multipliers can be created with the multiplier
mode (4 x 1 multiplier/PFU):
— 8 x 8 multiplier requires only 16 PFUs
— 30% increase in speed
Flip-op/latch options to allow programmable priority of
synchronous set/reset vs. clock enable
Enhanced cascadable nibble-wide data path
capabilities for adders, subtractors, counters, multipliers,
and comparators including internal fast-carry operation
Innovative, abundant, and hierarchical nibble-
oriented routing resources that allow automatic use of
internal gates for all device densities without sacricing
performance
Upward bit stream compatible with the ORCA ATT2Cxx/
ATT2Txx series of devices
Pinout-compatible with new ORCA Series 3 FPGAs
TTL or CMOS input levels programmable per pin for the
OR2CxxA (5 V) devices
Individually programmable drive capability:
12 mA sink/6 mA source or 6 mA sink/3 mA source
Built-in boundary scan (IEEE*1149.1 JTAG) and
3-state all I/O pins, (TS_ALL) testability functions
Multiple conguration options, including simple, low pin-
count serial ROMs, and peripheral or JTAG modes for in-
system programming (ISP)
Full PCI bus compliance for all devices
Supported by industry-standard CAE tools for design
entry, synthesis, and simulation with ORCA Foundry
Development System support (for back-end implementa-
tion)
New, added features (OR2TxxB) have:
— More I/O per package than the OR2TxxA family
— No dedicated 5 V supply (VDD5)
— Faster conguration speed (40 MHz)
— Pin selectable I/O clamping diodes provide 5V or 3.3V
PCI compliance and 5V tolerance
— Full PCI bus compliance in both 5V and 3.3V PCI sys-
tems
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Table 1. ORCA Series 2 FPGAs
Device
OR2C04A/OR2T04A
OR2C06A/OR2T06A
OR2C08A/OR2T08A
OR2C10A/OR2T10A
OR2C12A/OR2T12A
OR2C15A/OR2T15A/OR2T15B
OR2C26A/OR2T26A
OR2C40A/OR2T40A/OR2T40B
Usable
Gates*
4,800—11,000
6,900—15,900
9,400—21,600
12,300—28,300
15,600—35,800
19,200—44,200
27,600—63,600
43,200—99,400
# LUTs Registers
400
576
784
1024
1296
1600
2304
3600
400
576
724
1024
1296
1600
2304
3600
Max User
RAM Bits
6,400
9,216
12,544
16,384
20,736
25,600
36,864
57,600
User
I/Os
160
192
224
256
288
320
384
480
Array Size
10 x 10
12 x 12
14 x 14
16 x 16
18 x 18
20 x 20
24 x 24
30 x 30
* The rst number in the usable gates column assumes 48 gates per PFU (12 gates per four-input LUT/FF pair) for logic-only designs. The
second number assumes 30% of a design is RAM. PFUs used as RAM are counted at four gates per bit, with each PFU capable of
implementing a 16 x 4 RAM (or 256 gates) per PFU.

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OR2C06A equivalent
Data Sheet
January 2002
ORCA Series 2 FPGAs
ORCA Foundry Development System
Overview
The ORCA Foundry Development System interfaces to
front-end design entry tools and provides the tools to
produce a congured FPGA. In the design ow, the
user denes the functionality of the FPGA at two
points: at design entry and at the bit stream generation
stage.
Following design entry, the development system’s map,
place, and route tools translate the netlist into a routed
FPGA. Its bit stream generator is then used to generate
the conguration data which is loaded into the FPGA’s
internal conguration RAM. When using the bit stream
generator, the user selects options that affect the func-
tionality of the FPGA. Combined with the front-end
tools, ORCA Foundry produces conguration data that
implements the various logic and routing options dis-
cussed in this data sheet.
Architecture
The ORCA Series FPGA is comprised of two basic
elements: PLCs and PICs. Figure 1 shows an array of
programmable logic cells (PLCs) surrounded by pro-
grammable input/output cells (PICs). The Series 2 has
PLCs arranged in an array of 20 rows and 20 columns.
PICs are located on all four sides of the FPGA between
the PLCs and the IC edge.
The location of a PLC is indicated by its row and col-
umn so that a PLC in the second row and third column
is R2C3. PICs are indicated similarly, with PT (top) and
PB (bottom) designating rows and PL (left) and PR
(right) designating columns, followed by a number. The
routing resources and conguration RAM are not
shown, but the interquad routing blocks (hIQ, vIQ)
present in the Series 2 series are shown.
Each PIC contains the necessary I/O buffers to inter-
face to bond pads. The PICs also contain the routing
resources needed to connect signals from the bond
pads to/from PLCs. The PICs do not contain any user-
accessible logic elements, such as ip-ops.
Combinatorial logic is done in look-up tables (LUTs)
located in the PFU. The PFU can be used in different
modes to meet different logic requirements. The LUT’s
congurable medium-/large-grain architecture can be
used to implement from one to four combinatorial logic
functions. The exibility of the LUT to handle wide input
functions, as well as multiple smaller input functions,
maximizes the gate count/PFU.
The LUTs can be programmed to operate in one of
three modes: combinatorial, ripple, or memory. In com-
Lattice Semiconductor
binatorial mode, the LUTs can realize any four-, ve-,
or six-input logic functions. In ripple mode, the high-
speed carry logic is used for arithmetic functions, the
new multiplier function, or the enhanced data path
functions. In memory mode, the LUTs can be used as a
16 x 4 read/write or read-only memory (asynchronous
mode or the new synchronous mode) or a new 16 x 2
dual-port memory.
Programmable Logic Cells
The programmable logic cell (PLC) consists of a pro-
grammable function unit (PFU) and routing resources.
All PLCs in the array are identical. The PFU, which con-
tains four LUTs and four latches/FFs for logic imple-
mentation, is discussed in the next section.
Programmable Function Unit
The PFUs are used for logic. Each PFU has 19 exter-
nal inputs and six outputs and can operate in several
modes. The functionality of the inputs and outputs
depends on the operating mode.
The PFU uses three input data buses (A[4:0], B[4:0],
WD[3:0]), four control inputs (C0, CK, CE, LSR), and a
carry input (CIN); the last is used for fast arithmetic
functions. There is a 5-bit output bus (O[4:0]) and a
carry-out (COUT).
PROGRAMMABLE LOGIC CELL (PLC)
WD3
WD2
WD1
WD0
A4
A3
A2
A1
A0
B4
B3
B2
B1
B0
CIN
COUT
PROGRAMMABLE
FUNCTION UNIT
(PFU)
O4
O3
O2
O1
O0
C0 CK CE LSR
(ROUTING RESOURCES, CONFIGURATION RAM)
Figure 2. PFU Ports
5-2750(F).r3
5


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