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Número de pieza | SP5611 | |
Descripción | 13GHz Bidirectional I2C Bus Controlled Synthesiser | |
Fabricantes | Mitel Networks | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de SP5611 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
No Preview Available ! SP5611
1·3GHz Bidirectional I2C Bus Controlled Synthesiser
Advance Information
Supersedes February 1997 version, DS3758-4.1
DS3758 - 5.0 June 1998
The SP5611 is a single chip frequency synthesiser de-
signed for TV tuning systems. Control data is entered in the
standard I2C BUS format. The device contains 4 addressable
bidirectional open collector ports, one of which is a 3-bit ADC.
The information on these ports can be read via the I2C BUS.
the device has 4 programmable addresses, programmed by
applying a specific input voltage to the P3 address select
input. This enables two or more synthesisers to be used in a
system.
FEATURES
s Complete 1·3GHz Single Chip System
s High Sensitivity RF Inputs
s Programmable via I2C BUS
s Low Power Consumption (5V, 20mA)
s Low Radiation
s Phase Lock Detector
s Varactor Drive Amp Disable
s 4 Bi-directional Controllable Outputs
s 5-Level ADC
s Variable I2C BUS Address for Multi-tuner Applications
s ESD Protection: 4kV, Mil-Std-883C, Method 3015 (1)
s Switchable 4512/1024 Reference Divider
s Pin and Function Compatible with SP5511S (2)
(1) Normal ESD handling precautions should be observed.
(2) The SP5511S does not have a switchable reference
division ratio.
CHARGE PUMP
CRYSTAL Q1
CRYSTAL Q2
SDA
SCL
† I/O PORT P7
* I/O PORT P6
† I/O PORT P5
1 16
2 15
3 14
4 13
SP5611
5 12
6 11
7 10
89
DRIVE OUTPUT
VEE
RF INPUT
RF INPUT
VCC
NC
P3 ADD SELECT PORT
I/O PORT P4 †
MP16
† = Logic level I/O port
* = 3-bit ADC input
Fig. 1 Pin connections – top view
APPLICATIONS
s Satellite TV
s Cable Tuning Systems
s VCRs
THERMAL DATA
uJC = 41°C/W
uJA = 111°C/W
ORDERING INFORMATION
SP5611 KG/MPAS (Tubes)
SP5611S KG/MPAD (Tape and reel)
1 page SP5611
MSB
LSB
Address
Programmable divider
Programmable divider
1 1 0 0 0 MA1 MA0 0
0 214 213 212 211 210 29 28
27 26 25 24 23 22 21 20
Charge pump and test bits 1 CP T1 T0 TS2 TS1 TS0 OS
I/O port control bits
P7 P6 P5 P4 X X X X
Table 1 Write data format (MSB transmitted first)
A
A
A
A
A
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Address
Status byte
1 1 0 0 0 MA1 MA0 1 A Byte 1
POR FL I2 I1 I0 A2 A1 A0 A Byte 2
Table 2 Read data format
A2 A1 A0 Voltage input to P6
1 00
0 11
0 10
0 01
0 00
0·6VCC to 13·2V
0·45VCC to 0·6VCC
0·3VCC to 0·45VCC
0·15VCC to 0·3VCC
0V to 0·15VCC
Table 3 ADC levels
MA1 MA0 Address select input voltage
00
01
0V to 0·1VCC
Open circuit
10
0·4VCC to 0·6VCC
11
0·9VCC to VCC
Table 4 Address selection
T1 TS2 TS1 TS0
Operation mode description
0 X X 0 Normal operation, test modes disabled, reference divider ratio = 1024
0 X X 1 Normal operation, test modes disabled, reference divider ratio = 512
1 0 0 X Charge pump source (down). Status bit FL set to 0
1 0 1 X Charge pump sink (up). Status bit FL set to 1
1 1 0 0 Ports P4, P5, P6, P7set to state X
1 1 0 1 Port P7 = FPD/2; P4, P5, P6 set to state X
1 1 1 X Port P7 = FPD; P6 = FCOMP; P4, P5 set to state X
NOTES
Table 5 Operation modes
X = don’t care
For further details of test modes, see Table 6
A
MA1, MA0
CP
T1
T0
TS2, TS1, TS0
OS
P7, P6, P5, P4,
POR
FL
I2, I1, I0
A2, A1, A0
X
: Acknowledge bit
: Variable address bits (see Table 4)
: Charge Pump current select
: Test mode selection
: Charge pump disable
: Operation mode control bits (see Table 5)
: Varactor drive Output disable Switch
: Control output port states
: Power On Reset indicator
: Phase lock detect flag
: Digital information from ports P7, P5 and P4 respectively
: 5-level ADC data from P6 (see Table 3)
: Don’t care
Fig. 3 Data formats
5
5 Page 11 Page |
Páginas | Total 12 Páginas | |
PDF Descargar | [ Datasheet SP5611.PDF ] |
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