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74HC107 Datasheet PDF - Philips

Part Number 74HC107
Description Dual JK flip-flop with reset negative-edge trigger
Manufacturers Philips 
Logo Philips Logo 



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74HC107 datasheet, circuit
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT107
Dual JK flip-flop with reset;
negative-edge trigger
Product specification
File under Integrated Circuits, IC06
December 1990

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74HC107 equivalent
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
Product specification
74HC/HCT107
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: flip-flops
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
SYMBOL PARAMETER
74HC
+25 40 to +85 40 to +125
min. typ. max. min. max. min. max.
UNIT
VCC WAVEFORMS
(V)
tPHL/ tPLH
propagation delay
nCP to nQ
tPHL/ tPLH
propagation delay
nCP to nQ
52 160 200 240
2.0
19 32
40
48 ns
4.5 Fig.6
15 27 34 41
6.0
52 160 200 240
2.0
19 32
40
48 ns
4.5 Fig.6
15 27 34 41
6.0
tPHL/ tPLH
propagation delay
nR to nQ, nQ
52 155 195 235
2.0
19 31
39
47 ns
4.5 Fig.7
15 26 33 40
6.0
tTHL/ tTLH output transition time
tW
clock pulse width
HIGH or LOW
19 75
7 15
6 13
95
19
16
80 22
16 8
14 6
100
20
17
110
22
19
120
24
20
ns
ns
2.0
4.5 Fig.6
6.0
2.0
4.5 Fig.6
6.0
tW
reset pulse width
LOW
80 22
16 8
14 6
100 120
2.0
20 24 ns 4.5 Fig.7
17 20
6.0
trem
removal time
nR to nCP
60 19
12 7
10 6
tsu
set-up time
nJ, nK to nCP
100 22
20 8
17 6
th
hold time
nJ, nK to nCP
3 6
3 2
3 2
fmax
maximum clock pulse
frequency
6.0 23
30 70
35 85
75 90
2.0
15 18 ns 4.5 Fig.7
13 15
6.0
125 150
2.0
25 30 ns 4.5 Fig.6
21 26
6.0
33
2.0
3 3 ns 4.5 Fig.6
33
6.0
4.8 4.0
2.0
24 20 MHz 4.5 Fig.6
28 24
6.0
December 1990
5

5 Page
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Information Total 7 Pages
Download[ 74HC107.PDF Datasheet ]

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