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PDF 29EE010 Data sheet ( Hoja de datos )
| Número de pieza | 29EE010 | |
| Descripción | 1 Mbit (128K x8) Page-Mode EEPROM | |
| Fabricantes | Silicon Storage Technology | |
| Logotipo |  |
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1 Mbit (128K x8) Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
SST29EE010 / SST29LE010 / SST29VE0101Mb Page-Mode flash memories
FEATURES:
Data Sheet
• Single Voltage Read and Write Operations
– 5.0V-only for SST29EE010
– 3.0-3.6V for SST29LE010
– 2.7-3.6V for SST29VE010
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Current: 20 mA (typical) for 5V and 10 mA
(typical) for 3.0/2.7V
– Standby Current: 10 µA (typical)
• Fast Page-Write Operation
– 128 Bytes per Page, 1024 Pages
– Page-Write Cycle: 5 ms (typical)
– Complete Memory Rewrite: 5 sec (typical)
– Effective Byte-Write Cycle Time: 39 µs (typical)
• Fast Read Access Time
– 5.0V-only operation: 70 and 90 ns
– 3.0-3.6V operation: 150 and 200 ns
– 2.7-3.6V operation: 200 and 250 ns
• Latched Address and Data
• Automatic Write Timing
– Internal VPP Generation
• End of Write Detection
– Toggle Bit
– Data# Polling
• Hardware and Software Data Protection
• Product Identification can be accessed via
Software Operation
• TTL I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm, 8mm x 20mm)
– 32-pin PDIP
PRODUCT DESCRIPTION
The SST29EE/LE/VE010 are 128K x8 CMOS Page-Write
EEPROMs manufactured with SST’s proprietary, high per-
formance CMOS SuperFlash technology. The split-gate
cell design and thick oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches. The SST29EE/LE/VE010 write with a single
power supply. Internal Erase/Program is transparent to the
user. The SST29EE/LE/VE010 conform to JEDEC stan-
dard pinouts for byte-wide memories.
Featuring high performance Page-Write, the SST29EE/LE/
VE010 provide a typical Byte-Write time of 39 µsec. The
entire memory, i.e., 128 KBytes, can be written page-by-
page in as little as 5 seconds, when using interface features
such as Toggle Bit or Data# Polling to indicate the comple-
tion of a Write cycle. To protect against inadvertent write,
the SST29EE/LE/VE010 have on-chip hardware and Soft-
ware Data Protection schemes. Designed, manufactured,
and tested for a wide spectrum of applications, the
SST29EE/LE/VE010 are offered with a guaranteed Page-
Write endurance of 10,000 cycles. Data retention is rated at
greater than 100 years.
The SST29EE/LE/VE010 are suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applications,
the SST29EE/LE/VE010 significantly improve performance
and reliability, while lowering power consumption. The
SST29EE/LE/VE010 improve flexibility while lowering the
cost for program, data, and configuration storage applica-
tions.
To meet high density, surface mount requirements, the
SST29EE/LE/VE010 are offered in 32-lead PLCC and 32-
lead TSOP packages. A 600-mil, 32-pin PDIP package is
also available. See Figures 1, 2, and 3 for pinouts.
Device Operation
The SST Page-Mode EEPROM offers in-circuit electrical
write capability. The SST29EE/LE/VE010 does not require
separate Erase and Program operations. The internally
timed write cycle executes both erase and program trans-
parently to the user. The SST29EE/LE/VE010 have indus-
try standard optional Software Data Protection, which SST
recommends always to be enabled. The SST29EE/LE/
VE010 are compatible with industry standard EEPROM
pinouts and functionality.
©2001 Silicon Storage Technology, Inc.
S71061-07-000 6/01
304
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
SSF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
1 page  
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
A11
A9
A8
A13
A14
NC
WE#
VDD
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Standard Pinout
Top View
Die Up
FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP
32 OE#
31 A10
30 CE#
29 DQ7
28 DQ6
27 DQ5
26 DQ4
25 DQ3
24 VSS
23 DQ2
22 DQ1
21 DQ0
20 A0
19 A1
18 A2
17 A3
304 ILL F01.2
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6 32-pin
7 PDIP
8 Top View
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
304 ILL F19.0
FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP
TABLE 2: PIN DESCRIPTION
Symbol
A16-A7
A6-A0
DQ7-DQ0
Pin Name
Row Address Inputs
Column Address Inputs
Data Input/output
CE#
OE#
WE#
VDD
Chip Enable
Output Enable
Write Enable
Power Supply
VSS Ground
NC No Connection
Functions
To provide memory addresses. Row addresses define a page for a Write cycle.
Column Addresses are toggled to load page data
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide: 5.0V supply (±10%) for SST29EE010
3.0V supply (3.0-3.6V) for SST29LE010
2.7V supply (2.7-3.6V) for SST29VE010
Unconnected pins.
T2.1 304
©2001 Silicon Storage Technology, Inc.
5
S71061-07-000 6/01 304
5 Page 
1 Mbit Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
TABLE 13: PAGE-WRITE CYCLE TIMING PARAMETERS
SST29EE010
SST29LE/VE010
Symbol
Parameter
Min Max Min Max Units
TWC Write Cycle (Erase and Program)
10 10 ms
TAS Address Setup Time
0 0 ns
TAH Address Hold Time
50 70 ns
TCS WE# and CE# Setup Time
0 0 ns
TCH WE# and CE# Hold Time
0 0 ns
TOES
OE# High Setup Time
0 0 ns
TOEH
OE# High Hold Time
0 0 ns
TCP CE# Pulse Width
70 120 ns
TWP WE# Pulse Width
70 120 ns
TDS
TDH1
TBLC1
TBLCO1
TIDA1
Data Setup Time
Data Hold Time
Byte Load Cycle Time
Byte Load Cycle Time
Software ID Access and Exit Time
35 50
00
0.05 100 0.05 100
200 200
10 10
ns
ns
µs
µs
µs
TSCE
Software Chip-Erase
20 20 ms
T13.5 304
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
11
S71061-07-000 6/01 304
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet 29EE010.PDF ] | |
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