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What is 28F128?

This electronic component, produced by the manufacturer "Intel", performs the same function as "3 Volt Intel StrataFlash Memory".


28F128 Datasheet PDF - Intel

Part Number 28F128
Description 3 Volt Intel StrataFlash Memory
Manufacturers Intel 
Logo Intel Logo 


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3 Volt Intel® StrataFlashMemory
28F128J3A, 28F640J3A, 28F320J3A (x8/x16)
Preliminary Datasheet
Product Features
s High-Density Symmetrically-Blocked
Architecture
128 128-Kbyte Erase Blocks (128 M)
64 128-Kbyte Erase Blocks (64 M)
32 128-Kbyte Erase Blocks (32 M)
s High Performance Interface Asynchronous
Page Mode Reads
110/25 ns Read Access Time (32 M)
120/25 ns Read Access Time (64 M)
150/25 ns Read Access Time (128 M)
s 2.7 V3.6 V VCC Operation
s 128-bit Protection Register
64-bit Unique Device Identifier
64-bit User Programmable OTP Cells
s Enhanced Data Protection Features
Absolute Protection with VPEN = GND
Flexible Block Locking
Block Erase/Program Lockout during
Power Transitions
s Packaging
56-Lead TSOP Package
64-Ball Intel® Easy BGA Package
s Cross-Compatible Command Support Intel
Basic Command Set
Common Flash Interface
Scalable Command Set
s 32-Byte Write Buffer
6 µs per Byte Effective Programming
Time
s 12.8M Total Min. Erase Cycles (128 Mbit)
6.4M Total Min. Erase Cycles (64 Mbit)
3.2M Total Min. Erase Cycles (32 Mbit)
100K Minimum Erase Cycles per Block
s Automation Suspend Options
Block Erase Suspend to Read
Block Erase Suspend to Program
Program Suspend to Read
s 0.25 µ Intel® StrataFlashMemory
Technology
Capitalizing on Intel’s 0.25 µ generation two-bit-per-cell technology, second generation Intel®
StrataFlashmemory products provide 2X the bits in 1X the space, with new features for mainstream
performance. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, these devices bring
reliable, two-bit-per-cell storage technology to the flash market segment.
Benefits include: more density in less space, high-speed interface, lowest cost-per-bit NOR devices,
support for code and data storage, and easy migration to future devices.
Using the same NOR-based ETOXtechnology as Intels one-bit-per-cell products, Intel StrataFlash
memory devices take advantage of over one billion units of manufacturing experience since 1987. As a
result, Intel StrataFlash components are ideal for code and data applications where high density and low
cost are required. Examples include networking, telecommunications, digital set top boxes, audio
recording, and digital imaging.
By applying FlashFilememory family pinouts, Intel StrataFlash memory components allow easy design
migrations from existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation
Intel StrataFlash memory (28F640J5 and 28F320J5) devices.
Intel StrataFlash memory components deliver a new generation of forward-compatible software support.
By using the Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take
advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices.
Manufactured on Intel® 0.25 micron ETOXVI process technology, Intel StrataFlash memory provides
the highest levels of quality and reliability.
Notice: This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Order Number: 290667-008
April 2001

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28F128 equivalent
28F128J3A, 28F640J3A, 28F320J3A
Revision History
Date of Revision
07/07/99
08/03/99
09/07/99
12/16/99
03/16/00
06/26/00
2/15/01
04/13/01
Version
-001
-002
-003
-004
-005
-006
-007
-008
Description
Original Version
A0A2 indicated on block diagram
Changed Minimum Block Erase time,IOL, IOH, Page Mode and Byte
Mode currents. Modified RP# on AC Waveform for Write Operations
Changed Block Erase time and tAVWH
Removed all references to 5 V I/O operation
Corrected Ordering Information, Valid Combinations entries
Changed Min program time to 211 µs
Added DU to Lead Descriptions table
Changed Chip Scale Package to Ball Grid Array Package
Changed default read mode to page mode
Removed erase queuing from Figure 10, Block Erase Flowchart
Added Program Max time
Added Erase Max time
Added Max page mode read current
Moved tables to correspond with sections
Fixed typographical errors in ordering information and DC parameter
table
Removed VCCQ1 setting and changed VCCQ2/3 to VCCQ1/2
Added recommended resister value for STS pin
Change operation temperature range
Removed note that rp# could go to 14 V
Removed VOL of 0.45 V
Removed VOH of 2.4 V
Updated ICCR Typ values
Added Max lock-bit program and lock times
Added note on max measurements
Updated cover sheet statement of 700 million units to one billion.
Corrected Table 10 to show correct maximum program times.
Corrected error in Max block program time in section 6.7
Corrected typical erase time in section 6.7
Updated cover page to reflect 100K minimum erase cycles.
Updated cover page to reflect 110 ns 32M read speed.
Removed Set Read Configuration command from Table 4.
Updated Table 8 to reflect reserved bits are 1-7; not 2-7.
Updated Table 16 bit 2 definition from R to PSS.
Changed VPENLK Max voltage from 0.8 V to 2.0 V, Section 6.4, DC
Characteristics
Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Sec-
tion 6.5, AC Characteristics–Read-Only Operations (1,2)
Updated write parameter W13 (tWHRL) from 90 ns to 500 ns, Section
6.6, AC Characteristics–Write Operations
Updated Max. Program Suspend Latency W16 (tWHRH1) from 30 to 75
µs, Section 6.7, Block Erase, Program, and Lock-Bit Configuration Per-
formance (1,2,3)
Revised Section 7.0, Ordering Information
Preliminary
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