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What is 27C128?

This electronic component, produced by the manufacturer "Microchip Technology", performs the same function as "128K (16K x 8) CMOS EPROM".


27C128 Datasheet PDF - Microchip Technology

Part Number 27C128
Description 128K (16K x 8) CMOS EPROM
Manufacturers Microchip Technology 
Logo Microchip Technology Logo 


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27C128
128K (16K x 8) CMOS EPROM
FEATURES
• High speed performance
- 120 ns access time available
• CMOS Technology for low power consumption
- 20 mA Active current
- 100 µA Standby current
• Factory programming available
• Auto-insertion-compatible plastic packages
• Auto ID aids automated programming
• Separate chip enable and output enable controls
• High speed “express” programming algorithm
• Organized 16K x 8: JEDEC standard pinouts
- 28-pin Dual-in-line package
- 32-pin PLCC Package
- 28-pin SOIC package
- Tape and reel
• Available for the following temperature ranges:
- Commercial: 0˚C to +70˚C
- Industrial:
-40˚C to +85˚C
- Automotive:
-40˚C to +125˚C
DESCRIPTION
The Microchip Technology Inc. 27C128 is a CMOS
128K bit (electrically) Programmable Read Only Mem-
ory. The device is organized as 16K words by 8 bits
(16K bytes). Accessing individual bytes from an
address transition or from power-up (chip enable pin
going low) is accomplished in less than 120 ns. CMOS
design and processing enables this part to be used in
systems where reduced power consumption and high
reliability are requirements.A complete family of pack-
ages is offered to provide the most flexibility in applica-
tions. For surface mount applications, PLCC, SOIC, or
TSOP packaging is available. Tape and reel packaging
is also available for PLCC or SOIC packages. UV eras-
able versions are also available.
A complete family of packages is offered to provide the
most flexibility in applications. For surface mount appli-
cations, PLCC or SOIC packaging is available. Tape
and reel packaging is also available for PLCC or SOIC
packages.
PACKAGE TYPES
DIP/SOIC
VPP • 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
O0 11
O1 12
O2 13
VSS 14
28 VCC
27 PGM
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 O7
18 O6
17 O5
16 O4
15 O3
PLCC
A6 5
A5 6
A4 7
A3 8
A2 9
A1 10
A0 11
NC 12
O0 13
29 A8
28 A9
27 A11
26 NC
25 OE
24 A10
23 CE
22 O7
21 O6
© 1996 Microchip Technology Inc.
This document was created with FrameMaker 4 0 4
DS11003K-page 1

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27C128 equivalent
27C128
FIGURE 1-2: PROGRAMMING WAVEFORMS (1)
VIH
Address
VIL
VIH
Data
VIL
13.0 V (3)
VPP
5.0 V
Program
Address Stable
t AS
Data In Stable
tDS tDH
t VPS
High Z
Verify
tAH
Data Out Valid
tDF
(2)
6.5 V (3)
VCC
5.0 V
t VCS
VIH
CE
VIL
VIH
PGM
VIL
VIH
OE
VIL
t CES
t PW
t OPW
tOES
tOE
(2)
Notes: (1) The input timing reference is 0.8V for VIL and 2.0V for VIH.
(2) tDF and tOE are characteristics of the device but must be accommodated by the programmer.
(3) Vcc = 6.5V ±0.25V, VPP = VH = 13.0V ±0.25V for Express algorithm.
TABLE 1-6: MODES
Operation Mode
Read
Program
Program Verify
Program Inhibit
Standby
Output Disable
Identity
X = Don’t Care
CE
VIL
VIL
VIL
VIH
VIH
VIL
VIL
OE
VIL
VIH
VIL
X
X
VIH
VIL
PGM
VIH
VIL
VIH
X
X
VIH
VIH
VPP
VCC
VH
VH
VH
VCC
VCC
VCC
A9
X
X
X
X
X
X
VH
O0 - O7
DOUT
DIN
DOUT
High Z
High Z
High Z
Identity Code
1.2 Read Mode
(See Timing Diagrams and AC Characteristics)
Read Mode is accessed when
a) the CE pin is low to power up (enable) the chip
b) the OE pin is low to gate the data to the output
pins
For Read operations, if the addresses are stable, the
address access time (tACC) is equal to the delay from
CE to output (tCE). Data is transferred to the output
after a delay from the falling edge of OE (tOE).
© 1996 Microchip Technology Inc.
DS11003K-page 5


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