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What is DP8392?

This electronic component, produced by the manufacturer "National Semiconductor", performs the same function as "Coaxial Transceiver Interface".


DP8392 Datasheet PDF - National Semiconductor

Part Number DP8392
Description Coaxial Transceiver Interface
Manufacturers National Semiconductor 
Logo National Semiconductor Logo 


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May 1988
DP8392A NS32492A Coaxial Transceiver Interface
General Description
The DP8392A Coaxial Transceiver Interface (CTI) is a coax-
ial cable line driver receiver for Ethernet Thin Ethernet
(Cheapernet) type local area networks The CTI is connect-
ed between the coaxial cable and the Data Terminal Equip-
ment (DTE) In Ethernet applications the transceiver is usu-
ally mounted within a dedicated enclosure and is connected
to the DTE via a transceiver cable In Cheapernet applica-
tions the CTI is typically located within the DTE and con-
nects to the DTE through isolation transformers only The
CTI consists of a Receiver Transmitter Collision Detector
and a Jabber Timer The Transmitter connects directly to a
50 ohm coaxial cable where it is used to drive the coax
when transmitting During transmission a jabber timer is ini-
tiated to disable the CTI transmitter in the event of a longer
than legal length data packet Collision Detection circuitry
monitors the signals on the coax to determine the presence
of colliding packets and signals the DTE in the event of a
collision
The CTI is part of a three chip set that implements the com-
plete IEEE 802 3 compatible network node electronics as
shown below The other two chips are the DP8391 Serial
Network Interface (SNI) and the DP8390 Network Interface
Controller (NIC)
The SNI provides the Manchester encoding and decoding
functions whereas the NIC handles the Media Access Pro-
tocol and the buffer management tasks Isolation between
the CTI and the SNI is an IEEE 802 3 requirement that can
be easily satisfied on signal lines using a set of pulse trans-
formers that come in a standard DIP However the power
isolation for the CTI is done by DC-to-DC conversion
through a power transformer
Features
Y Compatible with Ethernet II IEEE 802 3 10Base5 and
10Base2 (Cheapernet)
Y Integrates all transceiver electronics except signal
power isolation
Y Innovative design minimizes external component count
Y Jabber timer function integrated on chip
Y Externally selectable CD Heartbeat allows operation
with IEEE 802 3 compatible repeaters
Y Precision circuitry implements receive mode collision
detection
Y Squelch circuitry at all inputs rejects noise
Y Designed for rigorous reliability requirements of
IEEE 802 3
Y Standard Outline 16-pin DIP uses a special leadframe
that significantly reduces the operating die temperature
Table of Contents
1 0 System Diagram
2 0 Block Diagram
3 0 Functional Description
3 1 Receiver and Squelch
3 2 Transmitter and Squelch
3 3 Collision and Heartbeat
3 4 Jabber Timer
4 0 Connection Diagram
5 0 Pin Descriptions
6 0 Absolute Maximum Ratings
7 0 Electrical Characteristics
8 0 Switching Characteristics
9 0 Timing and Load Diagram
10 0 Physical Dimensions
1 0 System Diagram
IEEE 802 3 Compatible Ethernet Cheapernet Local Area Network Chip Set
TL F 7405 – 1
C1995 National Semiconductor Corporation TL F 7405
RRD-B30M105 Printed in U S A

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DP8392 equivalent
5 0 Pin Descriptions
Pin No
Name
IO
Description
1
CDa
O Collision Output Balanced differential line driver outputs from the collision detect
2 CDb
circuitry The 10 MHz signal from the internal oscillator is transferred to these
outputs in the event of collision excessive transmission (jabber) or during CD
Heartbeat condition These outputs are open emitters pulldown resistors to VEE
are required When operating into a 78X transmission line these resistors should
be 500X In Cheapernet applications where the 78X drop cable is not used
higher resistor values (up to 1 5k) may be used to save power
3
RXa
O Receive Output Balanced differential line driver outputs from the Receiver These
6 RXb
outputs also require 500X pulldown resistors
7 TXa I Transmit Input Balanced differential line receiver inputs to the Transmitter The
8 TXb
common mode voltage for these inputs is determined internally and must not be
externally established Signals meeting Transmitter squelch requirements are
waveshaped and output at TXO
9 HBE I Heartbeat Enable This input enables CD Heartbeat when grounded disables it
when connected to VEE
11 RRa I External Resistor A fixed 1k 1% resistor connected between these pins
12 RRb
establishes internal operating currents
14 RXI
I Receive Input Connects directly to the coaxial cable Signals meeting Receiver
squelch requirements are equalized for inter-symbol distortion amplified and
outputted at RXg
15 TXO O Transmit Output Connects either directly (Cheapernet) or via an isolation diode
(Ethernet) to the coaxial cable
16 CDS
I Collision Detect Sense Ground sense connection for the collision detect circuit
This pin should be connected separately to the shield to avoid ground drops from
altering the receive mode collision threshold
10 GND
Positive Supply Pin A 0 1 mF ceramic decoupling capacitor must be connected
across GND and VEE as close to the device as possible
4 VEE
5
13
Negative Supply Pins In order to make full use of the 3 5W power dissipation
capability of this package these pins should be connected to a large metal frame
area on the PC board Doing this will reduce the operating die temperature of the
device thereby increasing the long term reliability
IEEE names for CDg e CIg RXg e DIg TXg e DOg
5 1 P C BOARD LAYOUT
The DP8392A package is uniquely designed to ensure that
the device meets the 1 million hour Mean Time Between
Failure (MTBF) requirement of the IEEE 802 3 standard In
order to fully utilize this heat dissipation design the three
VEE pins are to be connected to a copper plane which
should be included in the printed circuit board layout Refer
to National Semiconductor application note AN-442 (Ether-
net Cheapernet Physical Layer Made Easy) for complete
board layout instructions
5


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