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PDF BT8370 Data sheet ( Hoja de datos )

Número de pieza BT8370
Descripción single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces
Fabricantes Conexant Systems　
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Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
The Bt8370/8375/8376 is a family of single chip transceivers for T1/E1 and Integrated
Service Digital Network (ISDN) primary rate interfaces, operating at 1.544 Mbps or
2.048 Mbps. These devices combine a sophisticated framer, transmit and receive slip
buffers, and an on-chip physical line interface to provide a complete T1/E1 transceiver.
The fully featured Bt8370 and short-haul Bt8375 and Bt8376 devices provide a
programmable clock rate adapter for simplifying system bus interfacing. The adapter
synthesizes standard clock signals from the receive or transmit line rate clocks or from an
external reference.
Operations are controlled through memory-mapped registers accessible via a parallel
microprocessor port. Current ANSI, ETSI, ITU-T, and Bellcore standards are supported for
alarm and error monitoring, signaling supervision (e.g., LAPD/SS7), per-channel trunk
conditioning, and Facility Data Link (FDL) maintenance. A serial Time Division Multiplexed
(TDM) system bus interface allows the backplane Pulse Code Modulation (PCM) data
highway to operate at rates from 1.536 to 8.192 Mbps. Extensive test and diagnostic
functions include a full set of digital and analog loopbacks, PRBS test pattern generation,
BER meter, and forced error insertion.
The physical line interface circuit recovers clock and data from analog signals with +3 to
–43 dB cable attenuation, appropriate for both short (–18 dB) and long-haul T1/E1
applications. Receive line equalization (EQ) and transmit Line Build Out (LBO) filters are
implemented using Digital Signal Processor (DSP) circuits for reliable performance. Data
and/or clock jitter attenuation can be inserted on either the receive or transmit path. The
transmit section includes precision pulse shaping and amplitude pre-emphasis for cross
connect applications, as well as a set of LBO filters for long-haul Channel Service Unit
(CSU) applications. A complementary driver output is provided to couple 75/100/120 Ω
lines via an external transformer.
Functional Block Diagram
Distinguishing Features
• Single-chip T1/E1 framer with
short/long-haul physical line
interface
• Frames to popular T1/E1 standards:
– T1: SF, ESF, SLC96, T1DM
– E1: PCM-30, G.704, G.706, G.732
ISDN primary rate
• On-chip physical line interface
compatible with:
– DSX-1/E1 short-haul signals
– DS-1 (T1.403) and ETSI long-haul
signals
• Two-frame transmit and receive PCM
slip buffers
• Clock rate adapter synthesizes jitter
attenuated system clocks from an
internal or external reference
• Parallel 8-bit microprocessor port
supports Intel or Motorola buses
• Automated Facility Data Link (FDL)
management
• BERT generation and counting
• Two full-duplex HDLC controllers for
data link and LAPD/SS7 signaling
• B8ZS/HDB3/Bit 7 zero suppression
• 80-pin MQFP surface-mount package
• Operates from a single +5 Vdc ±5%
power supply
• Low-power CMOS technology
Receive
Analog
Transmit
Analog
RX EQ
RPLL
TPLL
Pulse
TX LBO
TX or RX
Jitter
Attenuator
ZCS
Decode
T1/E1
Receive
Framer
RX
Slip
Buffer
ZCS
Encode
TX
Slip
Buffer
Overhead
Insertion
T1/E1
Transmit
Framer
Receive
System
Bus
Transmit
System
Bus
Applications
• T1/E1 Channel Service Unit/Data
Service Unit (CSU/DSU)
• Digital Access Cross-Connect
Systems (DACS)
• T1/E1 Multiplexer (MUX)
• PBXs and PCM channel bank
• T1/E1 HDSL terminal unit
• ISDN Primary Rate Access (PRA)
JTAG
Control/Status
Registers
Data Link Controllers
DL1 + DL2
Clock Rate
Adaptor
Test Port
Motorola/Intel
Processor Bus
Dual-Rail/NRZ/
External DL3
CLAD I/O
Data Sheet
N8370DSE
June 30, 1999

1 page




BT8370 pdf
Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
Table of Contents
2.8.5 Test Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63
2.8.6 Transmit Error Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64
2.8.7 In-Band Loopback Code Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65
2.8.8 ZCS Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65
2.9 Transmit Line Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-68
2.9.1 Pulse Shape. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70
2.9.2 Transmit Phase Lock Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76
2.9.2.1 Clock Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76
2.9.2.2 Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-77
2.9.3 Line Build Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-77
2.9.4 Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80
2.9.4.1 Termination Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80
2.9.4.2 Return Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81
2.9.4.3 Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82
2.9.5 Pulse Imbalance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82
2.10 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-83
2.10.1 Address/Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-84
2.10.2 Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-84
2.10.3 Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-84
2.10.4 Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-85
2.10.4.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-85
2.10.4.2 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-85
2.10.4.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-85
2.11 Loopbacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-86
2.11.1 Remote Line Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-86
2.11.2 Remote Payload Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-86
2.11.3 Remote Per-Channel Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-86
2.11.4 Local Analog Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87
2.11.5 Local Framer Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87
2.11.6 Local Per-Channel Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87
2.12 Joint Test Access Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-88
2.12.1 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-88
2.12.2 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89
N8370DSE
Conexant
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5 Page





BT8370 arduino
Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
List of Figures
List of Figures
Figure 1-1.
Figure 1-2.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8.
Figure 2-9.
Figure 2-10.
Figure 2-11.
Figure 2-12.
Figure 2-13.
Figure 2-14.
Figure 2-15.
Figure 2-16.
Figure 2-17.
Figure 2-18.
Figure 2-19.
Figure 2-20.
Figure 2-21.
Figure 2-22.
Figure 2-23.
Figure 2-24.
Figure 2-25.
Figure 2-26.
Figure 2-27.
Figure 2-28.
Figure 2-29.
Figure 2-30.
Figure 2-31.
Figure 2-32.
Figure 2-33.
Figure 2-34.
Figure 2-35.
Figure 2-36.
Figure 2-37.
Bt8370/8375/8376 Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Bt8370/8375/8376 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Detailed Bt8370 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Detailed Bt8375 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Detailed Bt8376 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
RLIU Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
RLIU Waveforms—Bipolar Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
RLIU Waveforms—P and N Rail Digital Input Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Receive Input Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Jitter Attenuator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
CLAD/JAT Input Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
CLAD/JAT Jitter Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
RCVR Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Receive External Data Link Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
Polled Receive Data Link Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
Interrupt Driven Receive Data Link Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
RSB Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
RSB 4.096 MHz Bus Mode Time Slot Interleaving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
RSB 8.192 MHz Bus Mode Time Slot Interleaving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
RSB Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
T1 Line to E1 System Bus Time Slot Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
G.802 Embedded Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
Clock Rate Adapter/Jitter Attenuator Block Diagram (Bt8370 and Bt8375 Devices) . . . . . 2-40
Clock Rate Adapter/Jitter Attenuator Block Diagram (Bt8376 Device Only). . . . . . . . . . . . 2-41
TSB Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46
Transmit System Bus Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47
TSB 4.096 MHz Bus Mode Time Slot Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47
TSB 8.192 MHz Bus Mode Time Slot Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47
Transmit Framing and Timebase Alignment Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
XMTR Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53
Transmit External Data Link Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54
Polled Transmit Data Link Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57
Interrupt Driven Transmit Data Link Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58
Zero Code Substitution Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66
TLIU Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-68
TLIU Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69
Standard DS1 Pulse Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70
T1 Pulse Template Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70
Standard E1 (G.703) Pulse Template. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71
N8370DSE
Conexant
xi

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