P2V28S40ATP-7 Datasheet PDF - Vanguard International Semiconductor
Part Number | P2V28S40ATP-7 | |
Description | 128Mb SDRAM Specification | |
Manufacturers | Vanguard International Semiconductor  | |
Logo |   | |
There is a preview and P2V28S40ATP-7 download ( pdf file ) link at the bottom of this page. Total 51 Pages |
Preview 1 page No Preview Available ! 128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
128Mb SDRAM Specification
P2V28S20DTP-7,-75,-8
P2V28S30DTP-7,-75,-8
P2V28S40DTP-7,-75,-8
JULY.2000
MIRA TECHNOLOGY INC.
8F.,68,SEC.3,NANKING E.RD.,TAIPEI,TAIWAN,R.O.C.
TEL:886-2-25170055.25170066
FAX:886-2-25174575
Rev.2.2
|
|
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
PIN FUNCTION
CLK
Input
CKE
Input
/CS
/RAS, /CAS, /WE
Input
Input
A0-11
Input
Master Clock:
All other inputs are referenced to the rising edge of CLK
Clock Enable:
CKE controls internal clock.When CKE is low, internal clock for
the following cycle is ceased. CKE is also used to select
auto / self-refresh.
After self-refresh mode is started, CKE becomes asynchronous input.
Self-refresh is maintained as long as CKE is low.
Chip Select:
When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-11.
The Column Address is specified by A0-9,11(x4)/A0-9(x8)/A0-8(x16).
A10 is also used to indicate precharge option. When A10 is high at a
read / write command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
BA0,1
Input
Bank Address:
BA0,1 specifies one of four banks to which a command is applied.
BA0,1 must be set with ACT, PRE , READ , WRITE commands.
DQ0-3(x4),
DQ0-7(x8),
DQ0-15(x16)
Input / Output Data In and Data out are referenced to the rising edge of CLK.
DQM(x4,x8),
DQMU/L(x16)
Input
Din Mask / Output Disable:
When DQM(U/L) is high in burst write, Din for the current cycle is
masked. When DQM(U/L) is high in burst read,
Dout is disabled at the next but one cycle.
Vdd, Vss
VddQ, VssQ
Power Supply Power Supply for the memory array and peripheral circuitry.
Power Supply VddQ and VssQ are supplied to the Output Buffers only.
JULY.2000
Page-4
Rev.2.2
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for P2V28S40ATP-7 electronic component. |
Information | Total 51 Pages | |
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