PDF PSD834F2 Data sheet ( Hoja de datos )

Número de pieza	PSD834F2
Descripción	Flash In-System Programmable ISP Peripherals For 8-bit MCUs
Fabricantes	ST Microelectronics
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No Preview Available ! PSD8XXFX Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V Features ■ Flash in-system programmable (ISP) peripheral for 8-bit MCUs ■ Dual bank Flash memories )– Up to 2 Mbit of primary Flash memory (8 t(suniform sectors, 32K x8) c– Up to 256 Kbit secondary Flash memory (4 uuniform sectors) rod– Concurrent operation: read from one memory while erasing and writing the other P■ Up to 256 Kbit SRAM te■ 27 reconfigurable I/Oports ole■ Enhanced JTAG serial port s■ PLD with macrocells Ob– Over 3000 gates of PLD: CPLD and DPLD -– CPLD with 16 output macrocells (OMCs) )and 24 input macrocells (IMCs) t(s– DPLD - user defined internal chip select cdecoding du■ 27 individually configurable I/O port pins roThey can be used for the following functions: – MCU I/Os P– PLD I/Os te– Latched MCU address output le– Special function I/Os. so– 16 of the I/O ports may be configured as Ob open-drain outputs. PQFP52 (M) PLCC52 (J) TQFP64 (U) ■ Programmable power management ■ Packages are ECOPACK® Table 1. Device summary Reference Part number PSD813F2 PSD813F4 ■ In-system programming (ISP) with JTAG – Built-in JTAG compliant serial port allows PSD813F5 full-chip in-system programmability PSD8XXFX PSD833F2 – Efficient manufacturing allow easy product testing and programming – Use low cost FlashLINK cable with PC ■ Page register PSD834F2 PSD853F2 PSD854F2 – Internal page register that can be used to expand the microcontroller address space by a factor of 256 May 2009 Doc ID 7833 Rev 7 1/128 www.st.com 1 1 page PSD8XXFX Contents 16.17 OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 16.18 Input macro (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 16.19 Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 16.20 Ports A and B – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . 75 16.21 Port C – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 16.22 Port D – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 16.23 External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 17 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 )17.1 Automatic Power-down (APD) Unit and Power-down mode . . . . . . . . . . . 80 t(s17.2 For users of the HC11 (or compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 uc17.3 Other power saving options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 rod17.4 PLD power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 P17.5 PSD Chip Select input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 te17.6 Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ole17.7 Input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Obs18 Reset timing and device status at reset . . . . . . . . . . . . . . . . . . . . . . . . 85 ) -18.1 Power-up reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 t(s18.2 Warm reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 uc18.3 I/O pin, register and PLD status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . 85 rod18.4 Reset of Flash memory erase and program cycles (on the PSD834Fx) . 85 te P19 Programming in-circuit using the JTAG serial interface . . . . . . . . . . . 87 le19.1 Standard JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 so 19.2 JTAG extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Ob 19.3 Security and Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 20 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 21 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 22 AC/DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 23 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Doc ID 7833 Rev 7 5/128 5 Page PSD8XXFX 1 Summary description Summary description The PSD8XXFX family of memory systems for microcontrollers (MCUs) brings in-system- programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications. Table 2 summarizes all the devices. The CPLD in the PSD devices features an optimized macrocell logic architecture. The PSD macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD Obsolete Product(s) - Obsolete Product(s)Table 2. registers, to simplify communication between the MCU and other supporting devices. The PSD device includes a JTAG serial programming interface, to allow in-system programming (ISP) of the entire device. This feature reduces development time, simplifies the manufacturing flow, and dramatically lowers the cost of field upgrades. Using ST’s special Fast-JTAG programming, a design can be rapidly programmed into the PSD in as little as seven seconds. The innovative PSD8XXFX family solves key problems faced by designers when managing discrete Flash memory devices, such as: ● First-time in-system programming (ISP) ● Complex address decoding ● Simultaneous read and write to the device. The JTAG Serial Interface block allows in-system programming (ISP), and eliminates the need for an external Boot EPROM, or an external programmer. To simplify Flash memory updates, program execution is performed from a secondary Flash memory while the primary Flash memory is being updated. This solution avoids the complicated hardware and software overhead necessary to implement IAP. ST makes available a software development tool, PSDsoft™ Express, that generates ANSI- C compliant code for use with your target MCU. This code allows you to manipulate the non- volatile memory (NVM) within the PSD. Code examples are also provided for: ● Flash memory IAP via the UART of the host MCU ● Memory paging to execute code across several PSD memory pages ● Loading, reading, and manipulation of PSD macrocells by the MCU. Product range Primary Flash Secondary Part number(1) memory Flash memory (8 sectors) (4 sectors) SRAM I/O ports Number of macrocells Input Output Serial ISP JTAG/ISC port Turbo mode PSD813F2 PSD813F4 1 Mbit 1 Mbit 256 Kbit 256 Kbit 16 Kbit none 27 27 24 24 16 16 yes yes yes yes PSD813F5 PSD833F2 PSD834F2 1 Mbit 1 Mbit 2 Mbit none 256 Kbit 256 Kbit none 64 Kbit 64 Kbit 27 27 27 24 24 24 16 16 16 yes yes yes yes yes yes Doc ID 7833 Rev 7 11/128 11 Page

Páginas	Total 30 Páginas
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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
PSD834F2	Flash In-System Programmable ISP Peripherals For 8-bit MCUs	ST Microelectronics

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