8Q1024K8SRAM Datasheet PDF - Aeroflex Circuit Technology
Part Number | 8Q1024K8SRAM | |
Description | high-performance 1M byte (8Mbit) CMOS static RAM | |
Manufacturers | Aeroflex Circuit Technology | |
Logo | ||
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QCOTSTM UT8Q1024K8 SRAM
Data Sheet
January, 2003
FEATURES
25ns maximum (3.3 volt supply) address access time
Dual cavity package contains two (2) 512K x 8 industry-
standard asynchronous SRAMs; the control architecture
allows operation as an 8-bit data width
TTL compatible inputs and output levels, three-state
bidirectional data bus
Typical radiation performance
- Total dose: 50krad(Si)
- SEL Immune >80 MeV-cm2/mg
- LETTH(0.25) = >10 MeV-cm2/mg
- Saturated Cross Section cm2 per bit, 5.0E-9
- <1E-8 errors/bit-day, Adams 90% geosynchronous
heavy ion
Packaging options:
- 44-lead bottom brazed dual CFP (BBTFP) (4.6 grams)
Standard Microcircuit Drawing 5962-01532
- QML T and Q compliant part
INTRODUCTION
The QCOTSTM UT8Q1024K8 Quantified Commercial Off-the-
Shelf product is a high-performance 1M byte (8Mbit) CMOS
static RAM built with two individual 524,288 x 8 bit SRAMs
with a common output enable. Memory access and control is
provided by an active LOW chip enable (En), an active LOW
output enable (G). This device has a power-down feature that
reduces power consumption by more than 90% when deselected.
Writing to each memory is accomplished by taking one of the
chip enable (En) inputs LOW and write enable (Wn) inputs
LOW. Data on the I/O pins is then written into the location
specified on the address pins (A0 through A18). Reading from
the device is accomplished by taking one of the chip enable (En)
and output enable (G) LOW while forcing write enable (Wn)
HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
Only one SRAM can be read or written at a time.
The input/output pins are placed in a high impedance state when
the device is deselected (En HIGH), the outputs are disabled (G
HIGH), or during a write operation (En LOW and Wn LOW).
A(18:0)
G
E1 W1
E0 W0
512K x 8
512K x 8
DQ(7:0)
Figure 1. UT8Q1024K8 SRAM Block Diagram
1
|
|
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(-40°C to +125°C) (VDD = 3.3V + 0.3)
SYMBOL
PARAMETER
CONDITION
MIN
VIH High-level input voltage
(CMOS)
2.0
VIL Low-level input voltage
(CMOS)
VOL1 Low-level output voltage
IOL = 8mA, VDD =3.0V
VOL2 Low-level output voltage
IOL = 200µA,VDD =3.0V
VOH1 High-level output voltage
IOH = -4mA,VDD =3.0V
2.4
VOH2 High-level output voltage
IOH = -200µA,VDD =3.0V
VDD-0.10
CIN1 Input capacitance
ƒ = 1MHz @ 0V
CIO1 Bidirectional I/O capacitance
ƒ = 1MHz @ 0V
IIN Input leakage current
VSS < VIN < VDD, VDD = VDD (max)
-2
IOZ Three-state output leakage current 0V < VO < VDD
VDD = VDD (max)
G = VDD (max)
-2
I
2,
OS
3
Short-circuit output current
0V < VO < VDD
-90
IDD(OP) Supply current operating
@ 1MHz
Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
IDD1(OP) Supply current operating
@40MHz
IDD2(SB) Nominal standby supply current
@0MHz
Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
Inputs: VIL = VSS
IOUT = 0mA
En = VDD - 0.5,
VDD = VDD (max)
VIH = VDD - 0.5V
-40°C and 25°C
+125°C
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 101 9 .
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
MAX
0.8
0.4
0.08
20
24
2
2
90
150
220
4
25
UNIT
V
V
V
V
V
V
pF
pF
µA
µA
mA
mA
mA
mA
mA
5
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