87C453 Datasheet PDF - NXP Semiconductors
| Part Number | 87C453 | |
| Description | 80C51 8-bit microcontroller family 8K/256 OTP/ROM/ expanded I/O | |
| Manufacturers | NXP Semiconductors | |
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INTEGRATED CIRCUITS
83C453/87C453
80C51 8-bit microcontroller family
8K/256 OTP/ROM, expanded I/O
Preliminary specification
Supersedes data of 1997 Dec 29
IC20 Data Handbook
1998 Apr 23
Philips
Semiconductors
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Philips Semiconductors
80C51 8-bit microcontroller family
8K/256 OTP/ROM, expanded I/O
Preliminary specification
83C453/87C453
PIN DESCRIPTION
MNEMONIC
VSS
VCC
P0.0–0.7
PIN NO.
54
18
17-10
P1.0–P1.7
27-34
P2.0–P2.7
2-9
P3.0–P3.7
36-43
P4.0–P4.3
P4.0–P4.7
P5.0–P5.7
P6.0–P6.7
36
37
38
39
40
41
42
43
26-19
44-51
59-66
ODS
IDS
BFLAG
AFLAG
RST
ALE/PROG
55
56
57
58
35
68
PSEN
67
EA/VPP
XTAL1
XTAL2
1
53
52
TYPE NAME AND FUNCTION
I Ground: 0V reference.
I Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 is also the multiplexed data and low-order
address bus during accesses to external memory. External pull-ups are required during program
verification. Port 0 can sink/source eight LS TTL inputs.
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 receives the low-order address
bytes during program memory verification. Port 1 can sink/source three LS TTL inputs, and drive CMOS
inputs without external pull-ups.
I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 emits the high-order address
bytes during access to external memory and receives the high-order address bits and control signals
during program verification. Port 2 can sink/source three LS TTL inputs, and drive CMOS inputs without
external pull-ups.
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 can sink/source three LS TTL
inputs, and drive CMOS inputs without external pull-ups. Port 3 also serves the special functions listed
below:
I RxD (P3.0): Serial input port
O TxD (P3.1): Serial output port
I INT0 (P3.2): External interrupt
I INT1 (P3.3): External interrupt
I T0 (P3.4): Timer 0 external input
I T1 (P3.5): Timer 1 external input
O WR (P3.6): External data memory write strobe
O RD (P3.7): External data memory read strobe
I/O Port 4: Port 4 is an 8-bit bidirectional I/O port with internal pull-ups. Port 4 can sink/source three LS TTL
I/O inputs and drive CMOS inputs without external pull-ups.
I/O Port 5: Port 5 is an 8-bit bidirectional I/O port with internal pull-ups. Port 5 can sink/source three LS TTL
inputs and drive CMOS inputs without external pull-ups.
I/O Port 6: Port 6 is a specialized 8-bit bidirectional I/O port with internal pull-ups. This special port can
sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 6 can be used in a
strobed or non-strobed mode of operation. Port 6 works in conjunction with four control pins that serve the
functions listed below:
I ODS: Output data strobe
I IDS: Input data strobe
I/O BFLAG: Bidirectional I/O pin with internal pull-ups
I/O AFLAG: Bidirectional I/O pin with internal pull-ups
I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An
internal pull-down resistor permits a power-on reset using only an external capacitor connected to VCC.
I/O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an
access to external memory. ALE is activated at a constant rate of 1/6 the oscillator frequency except during
an external data memory access, at which time one ALE is skipped. ALE can sink/source three LS TTL
inputs and drive CMOS inputs without external pull-ups. This pin is also the program pulse during EPROM
programming.
O Program Store Enable: The read strobe to external program memory. PSEN is activated twice each
machine cycle during fetches from external program memory. However, when executing out of external
program memory, two activations of PSEN are skipped during each access to external program memory.
PSEN is not activated during fetches from internal program memory. PSEN can sink/source eight LS TTL
inputs and drive CMOS inputs without an external pull-up. This pin should be tied low during programming.
I Instruction Execution Control/Programming Supply Voltage: When EA is held high, the CPU executes
out of internal program memory, unless the program counter exceeds 1FFFH. When EA is held low, the
CPU executes out of external program memory. EA must never be allowed to float. This pin also receives
the 12.75V programming supply voltage (VPP) during EPROM programming.
I Crystal 1: Input to the inverting oscillator amplifier that forms the oscillator. This input receives the external
oscillator when an external oscillator is used.
O Crystal 2: An output of the inverting amplifier that forms the oscillator. This pin should be floated when an
external oscillator is used.
1998 Apr 23
5
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| Information | Total 26 Pages | |
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