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Número de pieza | 8405202XA | |
Descripción | CMOS 16-Bit Microprocessor | |
Fabricantes | Intersil Corporation | |
Logotipo | ![]() |
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80C86
March 1997
CMOS 16-Bit Microprocessor
[ /Title
(80C86
)
/Sub-
ject
(CMO
S 16-
Bit
Micro-
proces-
sor)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
Inter-
sil
Corpo-
ration,
16 Bit
uP,
micro-
proces-
sor,
8086,
PC)
/Cre-
Features
Description
• Compatible with NMOS 8086
• Completely Static CMOS Design
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C86)
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C86-2)
• Low Power Operation
- lCCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500µA Max
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 10mA/MHz Typ
• 1MByte of Direct Memory Addressing Capability
• 24 Operand Addressing Modes
• Bit, Byte, Word and Block Move Operations
• 8-Bit and 16-Bit Signed/Unsigned Arithmetic
- Binary, or Decimal
- Multiply and Divide
• Wide Operating Temperature Range
- C80C86 . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
- l80C86 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M80C86 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
The Intersil 80C86 high performance 16-bit CMOS CPU is
manufactured using a self-aligned silicon gate CMOS pro-
cess (Scaled SAJI IV). Two modes of operation, minimum for
small systems and maximum for larger applications such as
multiprocessing, allow user configuration to achieve the
highest performance level. Full TTL compatibility (with the
exception of CLOCK) and industry standard operation allow
use of existing NMOS 8086 hardware and software designs.
Ordering Information
PACKAGE
PDIP
PLCC
CERDIP
SMD#
CLCC
SMD#
TEMP. RANGE 5MHz
8MHz
PKG.
NO.
0oC to +70oC CP80C86 CP80C86-2 E40.6
-40oC to +85oC lP80C86 IP80C86-2 E40.6
0oC to +70oC CS80C86 CS80C86-2 N44.65
-40oC to +85oC lS80C86 IS80C86-2 N44.65
0oC to +70oC CD80C86 CD80C86-2 F40.6
-40oC to +85oC ID80C86 ID80C86-2 F40.6
-55oC to +125oC MD80C86/B MD80C86- F40.6
2/B
-55oC to +125oC 8405201QA 8405202QA F40.6
-55oC to +125oC MR80C86/B MR80C86- J44.A
2/B
-55oC to +125oC 8405201XA 8405202XA J44.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
3-141
File Number 2957.1
1 page ![]() ![]() 80C86
Pin Description (Continued)
The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is
the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
INTR
18
I INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle
of each instruction to determine if the processor should enter into an interrupt acknowledge op-
eration. A subroutine is vectored to via an interrupt vector lookup table located in system mem-
ory. It can be internally masked by software resetting the interrupt enable bit.
lNTR is internally synchronized. This signal is active HIGH.
TEST
23
I TEST: input is examined by the “Wait” instruction. If the TEST input is LOW execution continues,
otherwise the processor waits in an “Idle” state. This input is synchronized internally during each
clock cycle on the leading edge of CLK.
NMI 17
I NON-MASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A
subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is
not maskable internally by software. A transition from LOW to HIGH initiates the interrupt at the
end of the current instruction. This input is internally synchronized.
RESET
21
I RESET: causes the processor to immediately terminate its present activity. The signal must tran-
sition LOW to HIGH and remain active HIGH for at least four clock cycles. It restarts execution,
as described in the Instruction Set description, when RESET returns LOW. RESET is internally
synchronized.
CLK 19
I CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a
33% duty cycle to provide optimized internal timing.
VCC
40
VCC: +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 is recommended for de-
coupling.
GND
1, 20
GND: Ground. Note: both must be connected. A 0.1µF capacitor between pins 1 and 20 is rec-
ommended for decoupling.
MN/MX
33
I MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are
discussed in the following sections.
Minimum Mode System
The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = VCC). Only the pin functions which are unique to
minimum mode are described; all other pin functions are as described below.
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
M/IO
28
O STATUS LINE: logically equivalent to S2 in the maximum mode. It is used to distinguish a mem-
ory access from an I/O access. M/lO becomes valid in the T4 preceding a bus cycle and remains
valid until the final T4 of the cycle (M = HIGH, I/O = LOW). M/lO is held to a high impedance logic
one during local bus “hold acknowledge”.
WR 29 O WRITE: indicates that the processor is performing a write memory or write I/O cycle, depending
on the state of the M/IO signal. WR is active for T2, T3 and TW of any write cycle. It is active
LOW, and is held to high impedance logic one during local bus “hold acknowledge”.
INTA
24
O INTERRUPT ACKNOWLEDGE: is used as a read strobe for interrupt acknowledge cycles. It is
active LOW during T2, T3 and TW of each interrupt acknowledge cycle. Note that INTA is never
floated.
ALE 25
O ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the
82C82/82C83 address latch. It is a HIGH pulse active during clock LOW of T1 of any bus cycle.
Note that ALE is never floated.
3-145
5 Page ![]() ![]() 80C86
CLK
ALE
S2-S0
(4 + NWAIT) = TCY
(4 + NWAIT) = TCY
T1 T2 T3 TWAIT T4 T1 T2 T3 TWAIT T4
GOES INACTIVE IN THE STATE
JUST PRIOR TO T4
ADDR/
STATUS
ADDR/DATA
RD, INTA
READY
DT/R
DEN
WR
BHE,
A19-A16
A15-A0
S7-S3
BUS RESERVED
FOR DATA IN
D15-D0
VALID
BHE
A19-A16
S7-S3
A15-A0
DATA OUT (D15-D0)
READY
WAIT
READY
WAIT
MEMORY ACCESS TIME
FIGURE 3. BASIC SYSTEM TIMING
3-151
11 Page |
Páginas | Total 30 Páginas | |
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