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PDF 82434NX Data sheet ( Hoja de datos )
| Número de pieza | 82434NX | |
| Descripción | PCI/ CACHE AND MEMORY CONTROLLER PCMC | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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82434LX 82434NX PCI CACHE AND MEMORY
CONTROLLER (PCMC)
Y Supports the PentiumTM Processor at
iCOMPTM Index 510T60 MHz and iCOMP
Index 567T66 MHz
Y Supports the Pentium Processor at
iCOMP Index 735T90 MHz iCOMP Index
815T100 MHz and iCOMP Index 610T75
MHz
Y Supports Pipelined Addressing
Capability of the Pentium Processor
Y The 82430NX Drives 3 3V Signal Levels
on the CPU and Cache Interfaces
Y High Performance CPU PCI Memory
Interfaces via Posted Write and Read
Prefetch Buffers
Y Fully Synchronous PCI Interface with
Full Bus Master Capability
Y Supports the Pentium Processor
Internal Cache in Either Write-Through
or Write-Back Mode
Y Programmable Attribute Map of DOS
and BIOS Regions for System
Flexibility
Y Integrated Low Skew Clock Driver for
Distributing Host Clock
Y Integrated Second Level Cache
Controller
Integrated Cache Tag RAM
Write-Through and Write-Back Cache
Modes for the 82434LX
Write-Back for the 82434NX
82434NX Supports Low-Power Cache
Standby
Direct Mapped Organization
Supports Standard and Burst SRAMs
256-KByte and 512-KByte Sizes
Cache Hit Cycle of 3-1-1-1 on Reads
and Writes Using Burst SRAMs
Cache Hit Cycle of 3-2-2-2 on Reads
and 4-2-2-2 on Writes Using
Standard SRAMs
Y Integrated DRAM Controller
Supports 2 MBytes to 192 MBytes of
Cacheable Main Memory for the
82434LX
Supports 2 MBytes to 512 MBytes of
Cacheable Main Memory for the
82434NX
Supports DRAM Access Times of
70 ns and 60 ns
CPU Writes Posted to DRAM 4-1-1-1
Refresh Cycles Decoupled from ISA
Refresh to Reduce the DRAM
Access Latency
Six RAS Lines (82434LX)
Eight RAS Lines (82434NX)
Refresh by RAS -Only or CAS-
Before-RAS in Single or Burst
of Four
Y Host PCI Bridge
Translates CPU Cycles into PCI Bus
Cycles
Translates Back-to-Back Sequential
CPU Memory Writes into PCI Burst
Cycles
Burst Mode Writes to PCI in Zero PCI
Wait-States (i e Data Transfer Every
Cycle)
Full Concurrency Between CPU-to-
Main Memory and PCI-to-PCI
Transactions
Full Concurrency Between CPU-to-
Second Level Cache and PCI-to-Main
Memory Transactions
Same Cache and Memory System
Logic Design for ISA and EISA
Systems
Cache Snoop Filter Ensures Data
Consistency for PCI-to-Main Memory
Transactions
Y 208-Pin QFP Package
Other brands and names are the property of their respective owners
December 1994
Order Number 290479-004
1 page  
CONTENTS
3 2 4 PCICMD PCI COMMAND REGISTER
3 2 5 PCISTS PCI STATUS REGISTER
3 2 6 RID REVISION IDENTIFICATION REGISTER
3 2 7 RLPI REGISTER-LEVEL PROGRAMMING INTERFACE REGISTER
3 2 8 SUBC SUB-CLASS CODE REGISTER
3 2 9 BASEC BASE CLASS CODE REGISTER
3 2 10 MLT MASTER LATENCY TIMER REGISTER
3 2 11 BIST BIST REGISTER
3 2 12 HCS HOST CPU SELECTION REGISTER
3 2 13 DFC DETURBO FREQUENCY CONTROL REGISTER
3 2 14 SCC SECONDARY CACHE CONTROL REGISTER
3 2 15 HBC HOST READ WRITE BUFFER CONTROL
3 2 16 PBC PCI READ WRITE BUFFER CONTROL REGISTER
3 2 17 DRAMC DRAM CONTROL REGISTER
3 2 18 DRAMT DRAM TIMING REGISTER
3 2 19 PAM PROGRAMMABLE ATTRIBUTE MAP REGISTERS (PAM 6 0 )
3 2 20 DRB DRAM ROW BOUNDARY REGISTERS
3 2 20 1 82434LX Description
3 2 20 2 82434NX Description
3 2 21 DRBE DRAM ROW BOUNDARY EXTENSION REGISTER
3 2 22 ERRCMD ERROR COMMAND REGISTER
3 2 23 ERRSTS ERROR STATUS REGISTER
3 2 24 SMRS SMRAM SPACE REGISTER
3 2 25 MSG MEMORY SPACE GAP REGISTER
3 2 26 FBR FRAME BUFFER RANGE REGISTER
4 0 PCMC ADDRESS MAP
4 1 CPU Memory Address Map
4 2 System Management RAM
4 3 PC Compatibility Range
4 4 I O Address Map
SMRAM
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5 Page 
82434LX 82434NX
Figure 1 Block Diagram of a 82430LX 82430NX PCIset ISA System
290479 – 2
PCI Bus
The PCI Bus is designed to address the growing in-
dustry needs for a standardized local bus that is not
directly dependent on the speed and the size of the
processor bus New generations of personal com-
puter system software such as WindowsTM and
Win-NTTM with sophisticated graphical interfaces
multi-tasking and multi-threading bring new require-
ments that traditional PC I O architectures cannot
satisfy In addition to the higher bandwidth reliability
and robustness of the I O subsystem are becoming
increasingly important PCI addresses these needs
and provides a future upgrade path PCI features in-
clude
Processor independent
Multiplexed burst mode operation
Synchronous at frequencies up to 33 MHz
120 MByte sec usable throughput
(132 MByte sec peak) for a 32-bit data path
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 82434NX.PDF ] | |
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