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What is 80C88?

This electronic component, produced by the manufacturer "Intersil Corporation", performs the same function as "CMOS 8/16-Bit Microprocessor".


80C88 Datasheet PDF - Intersil Corporation

Part Number 80C88
Description CMOS 8/16-Bit Microprocessor
Manufacturers Intersil Corporation 
Logo Intersil Corporation Logo 


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80C88
March 1997
CMOS 8/16-Bit Microprocessor
[ /Title
(80C88
)
/Sub-
ject
(CMO
S 8/16-
Bit
Micro-
proces-
sor)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
8/16
Bit uP,
micro-
proces-
sor, 8
bit, 16
bit, 8-
bit, 16-
bit,
8088,
PC)
/Cre-
ator ()
Features
Description
• Compatible with NMOS 8088
• Direct Software Compatibility with 80C86, 8086, 8088
• 8-Bit Data Bus Interface; 16-Bit Internal Architecture
• Completely Static CMOS Design
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C88)
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C88-2)
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . 500µA Maximum
- ICCOP . . . . . . . . . . . . . . . . . . . . 10mA/MHz Maximum
• 1 Megabyte of Direct Memory Addressing Capability
The Intersil 80C88 high performance 8/16-bit CMOS CPU is
manufactured using a self-aligned silicon gate CMOS pro-
cess (Scaled SAJI IV). Two modes of operation, MINimum
for small systems and MAXimum for larger applications such
as multiprocessing, allow user configuration to achieve the
highest performance level.
Full TTL compatibility (with the exception of CLOCK) and
industry-standard operation allow use of existing NMOS
8088 hardware and Intersil CMOS peripherals.
Complete software compatibility with the 80C86, 8086, and
8088 microprocessors allows use of existing software in new
designs.
• 24 Operand Addressing Modes
• Bit, Byte, Word, and Block Move Operations
• 8-Bit and 16-Bit Signed/Unsigned Arithmetic
• Bus-Hold Circuitry Eliminates Pull-up Resistors
• Wide Operating Temperature Ranges
- C80C88 . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to + 70oC
- I80C88 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M80C88 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Ordering Information
PACKAGE
Plastic DIP
PLCC
CERDIP
SMD#
LCC
SMD#
TEMPERATURE RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
5MHz
CP80C88
IP80C88
CS80C88
lS80C88
CD80C88
ID80C88
MD80C88/B
5962-8601601QA
MR80C88/B
5962-8601601XA
8MHz
CP80C88-2
IP80C88-2
CS80C88-2
IS80C88-2
CD80C88-2
ID80C88-2
MD80C88-2/B
-
MR80C88-2/B
-
PKG. NO.
E40.6
E40.6
N44.65
N44.65
F40.6
F40.6
F40.6
F40.6
J44.A
J44.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
3-1
File Number 2949.1

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80C88 equivalent
80C88
Pin Description (Continued)
The following pin function descriptions are for 80C88 system in minimum mode (i.e., MN/MX = VCC). Only the pin functions
which are unique to the minimum mode are described; all other pin functions are as described above.
MINIMUM MODE SYSTEM
PIN
SYMBOL NUMBER TYPE
DESCRIPTION
IO/M 28 O STATUS LINE: is an inverted maximum mode S2. It is used to distinguish a memory access from
an I/O access. IO/M becomes valid in the T4 preceding a bus cycle and remains valid until the final
T4 of the cycle (I/O = HIGH, M = LOW). IO/M is held to a high impedance logic one during local bus
“hold acknowledge”.
WR 29 O Write: strobe indicates that the processor is performing a write memory or write I/O cycle, depend-
ing on the state of the IO/M signal. WR is active for T2, T3, and Tw of any write cycle. It is active
LOW, and is held to high impedance logic one during local bus “hold acknowledge”.
INTA 24 O INTA: is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3 and
Tw of each interrupt acknowledge cycle. Note that INTA is never floated.
ALE 25 O ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the
82C82/82C83 address latch. It is a HIGH pulse active during clock low of T1 of any bus cycle. Note
that ALE is never floated.
DT/R 27 O DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use an 82C86/82C87
data bus transceiver. It is used to control the direction of data flow through the transceiver. Logically,
DT/R is equivalent to S1 in the maximum mode, and its timing is the same as for IO/M (T = HIGH,
R = LOW). This signal is held to a high impedance logic one during local bus “hold acknowledge”.
DEN 26 O DATA ENABLE: is provided as an output enable for the 82C86/82C87 in a minimum system which
uses the transceiver. DEN is active LOW during each memory and I/O access, and for INTA cycles.
For a read or INTA cycle, it is active from the middle of T2 until the middle of T4, while for a write
cycle, it is active from the beginning of T2 until the middle of T4. DEN is held to high impedance logic
one during local bus “hold acknowledge”.
HOLD,
HLDA
31
30
I HOLD: indicates that another master is requesting a local bus “hold”. To be acknowledged, HOLD
O must be active HIGH. The processor receiving the “hold” request will issue HLDA (HIGH) as an
acknowledgment, in the middle of a T4 or T1 clock cycle. Simultaneous with the issuance of HLDA
the processor will float the local bus and control lines. After HOLD is detected as being LOW, the
processor lowers HLDA, and when the processor needs to run another cycle, it will again drive the
local bus and control lines.
Hold is not an asynchronous input. External synchronization should be provided if the system cannot
otherwise guarantee the set up time.
SS0 34 O STATUS LINE: is logically equivalent to S0
in the maximum mode. The combination of IO/M DT/R SS0 CHARACTERISTICS
SS0, IO/M and DT/R allows the system to
completely decode the current bus cycle
status. SS0 is held to high impedance logic
1
1
0 0 Interrupt Acknowledge
0 1 Read I/O Port
one during local bus “hold acknowledge”.
1 1 0 Write I/O Port
1 1 1 Halt
0 0 0 Code Access
0 0 1 Read Memory
0 1 0 Write Memory
0 1 1 Passive
3-5


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