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PDF MAX196 Data sheet ( Hoja de datos )
| Número de pieza | MAX196 | |
| Descripción | Multirange / Single %V / 12-Bit DAS with 12-Bit Bus Interface | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX196 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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19-0435; Rev 0; 9/95
EVAALVUAAILTAIOBNLEKIT
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
_______________General Description
The MAX196/MAX198 multirange, 12-bit data-acquisi-
tion systems (DAS) require only a single +5V supply for
operation, yet convert analog signals at their inputs up
to ±10V (MAX196) and ±4V (MAX198). These systems
provide six analog input channels that are indepen-
dently software programmable for a variety of ranges:
±10V, ±5V, 0V to +10V, and 0V to +5V for the MAX196;
±VREF, ±VREF/2, 0V to +VREF, and 0V to +VREF/2 for
the MAX198. This range switching increases the effec-
tive dynamic range to 14 bits and provides the flexibility
to interface ±12V, ±15V, and 4mA to 20mA powered
sensors to a single +5V system. In addition, these con-
verters are fault protected to ±16.5V; a fault condition
on any channel will not affect the conversion result of
the selected channel. Other features include a 5MHz
bandwidth track/hold, 100ksps throughput rate, soft-
ware-selectable internal/external clock, internal/external
acquisition control, 12-bit parallel interface, and internal
4.096V or external reference.
Two programmable power-down modes (STBYPD,
FULLPD) provide low-current shutdown between con-
versions. In STBYPD mode, the reference buffer
remains active, eliminating start-up delays.
The MAX196/MAX198 employ a standard microproces-
sor (µP) interface. A three-state data I/O port is config-
ured to operate with 16-bit data buses, and data-
access and bus-release timing specifications are com-
patible with most popular µPs. All logic inputs and out-
puts are TTL/CMOS compatible.
These devices are available in 28-pin DIP, wide SO,
SSOP (55% smaller in area than wide SO), and ceramic
SB packages. For 8+4 bus interface, see the MAX197
and the MAX199 data sheets. An evaluation kit will be
available after December 1995 (MAX196EVKIT-DIP).
________________________Applications
Industrial-Control Systems
Robotics
Data-Acquisition Systems
Automatic Testing Systems
Medical Instruments
Telecommunications
Functional Diagram appears at end of data sheet.
____________________________Features
o 12-Bit Resolution, 1/2LSB Linearity
o Single +5V Supply Operation
o Software-Selectable Input Ranges:
±10V, ±5V, 0V to +10V, 0V to +5V (MAX196)
±VREF, ±VREF/2, 0V to +VREF, 0V to +VREF/2
(MAX198)
o Internal 4.096V or External Reference
o Fault-Protected Input Multiplexer
o 6 Analog Input Channels
o 6µs Conversion Time, 100ksps Sampling Rate
o Internal or External Acquisition Control
o Two Power-Down Modes
o Internal or External Clock
______________Ordering Information
PART
TEMP. RANGE PIN-PACKAGE
MAX196ACNI 0°C to +70°C 28 Narrow Plastic DIP
MAX196BCNI 0°C to +70°C 28 Narrow Plastic DIP
MAX196ACWI 0°C to +70°C 28 Wide SO
MAX196BCWI 0°C to +70°C 28 Wide SO
MAX196ACAI 0°C to +70°C 28 SSOP
MAX196BCAI 0°C to +70°C 28 SSOP
Ordering Information continued at end of data sheet.
__________________Pin Configuration
TOP VIEW
CLK 1
CS 2
D11 3
D10 4
D9 5
D8 6
D7 7
D6 8
D5 9
D4 10
D3 11
D2 12
D1 13
D0 14
MAX196
MAX198
28 DGND
27 VDD
26 WR
25 RD
24 INT
23 REF
22 REFADJ
21 CH5
20 CH4
19 CH3
18 CH2
17 CH1
16 CH0
15 AGND
DIP/SO/SSOP/Ceramic SB
________________________________________________________________ Maxim Integrated Products 1
Call toll free 1-800-722-8266 for free samples or literature.
1 page  
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz
with 50% duty cycle; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
DIGITAL OUTPUTS (D11–D0, INT)
Output Low Voltage
Output High Voltage
Three-State Output Capacitance
VOL
VOH
COUT
VDD = 4.75V, ISINK = 1.6mA
VDD = 4.75V, ISOURCE = 1mA
(Note 5)
VDD - 1
0.4 V
V
15 pF
TIMING CHARACTERISTICS
(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz
with 50% duty cycle; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
CS Pulse Width
WR Pulse Width
CS to WR Setup Time
CS to WR Hold Time
CS to RD Setup Time
CS to RD Hold Time
CLK to WR Setup Time
CLK to WR Hold Time
Data Valid to WR Setup
Data Valid to WR Hold
RD Low to Output Data Valid
RD High to Output Disable
RD Low to INT High Delay
SYMBOL
tCS
tWR
tCSWS
tCSWH
tCSRS
tCSRH
tCWS
tCWH
tDS
tDH
tDO
tTR
tINT1
CONDITIONS
Figure 2, CL = 100pF (Note 12)
(Note 13)
MIN TYP MAX UNITS
80 ns
80 ns
0 ns
0 ns
0 ns
0 ns
100 ns
50 ns
60 ns
0 ns
120 ns
70 ns
120 ns
Note 1: Accuracy specifications tested at VDD = 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply
Rejection test. Tested for the ±10V (MAX196) and ±4.096V (MAX198) input ranges.
Note 2: External reference: VREF = 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB.
Note 3: Ground “on” channel; sine wave applied to all “off” channels.
Note 4: Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.
Note 5: Guaranteed by design. Not tested.
Note 6: Use static loads only.
Note 7: Tested using internal reference.
Note 8: PSRR measured at full-scale.
Note 9: External acquisition timing: starts at data valid at ACQMOD = low control byte; ends at rising edge of WR with ACQMOD
= high control byte.
Note 10: Not subject to production testing. Provided for design guidance only.
Note 11: All input control signals specified with tR = tF = 5ns from a voltage level of 0.8V to 2.4V.
Note 12: tDO is measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 13: tTR is defined as the time required for the data lines to change by 0.5V.
_______________________________________________________________________________________ 5
5 Page 
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
tCS
CS
tCSWS
WR
D7–D0
tWR
tDS
CONTROL
BYTE
ACQMOD = "1"
tCSHtAWCQI
tCONV
tDH
CONTROL
BYTE
ACQMOD = "0"
INT
tCSRS
tINT1
tCSRH
RD
DOUT
tD0 tTR
DATA VALID
Figure 6. Conversion Timing Using External Acquisition Mode
Clock Modes
The MAX196/MAX198 operate with either an internal or
an external clock. Control bits (D6, D7) select either
internal or external clock mode. Once the desired clock
mode is selected, changing these bits to program
power-down will not affect the clock mode. In each
mode, internal or external acquisition can be used. At
power-up, external clock mode is selected.
Internal Clock Mode
Select internal clock mode to free the µP from the
burden of running the SAR conversion clock. To select
this mode, write the control byte with D7 = 0 and D6 =
1. A 100pF capacitor between the CLK pin and ground
sets this frequency to 1.56MHz nominal. Figure 7
shows a linear relationship between the internal clock
period and the value of the external capacitor used.
External Clock Mode
Select external clock mode by writing the control byte
with D7 = 0 and D6 = 0. Figure 8 shows CLK and WR
timing relationships in internal and external acquisition
modes, with an external clock. A 100kHz to 2.0MHz
external clock with 45% to 55% duty cycle is required for
proper operation. Operating at clock frequencies lower
than 100kHz will cause a voltage droop across the hold
capacitor, and subsequently degrade performance.
2000
1500
1000
500
0
0 50 100 150 200 250 300 350
CLOCK PIN CAPACITANCE (pF)
Figure 7. Internal Clock Period vs. Clock Pin Capacitance
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MAX196.PDF ] | |
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