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PDF MAX1201 Data sheet ( Hoja de datos )
| Número de pieza | MAX1201 | |
| Descripción | +5v sINGLE-sUPPLY / 2.2mSPS / 14-bIT sELF-cALIBRATING adc | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX1201 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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19-4776; Rev 1; 11/98
EVAALVUAAILTAIOBNLEKIT
+5V Single-Supply, 2.2Msps, 14-Bit
Self-Calibrating ADC
General Description
The MAX1201 is a 14-bit, monolithic, analog-to-digital
converter (ADC) capable of conversion rates up to
2.2Msps. This integrated circuit, built on a CMOS
process, uses a fully differential, pipelined architecture
with digital error correction and a short self-calibration
procedure that corrects for capacitor and gain mis-
matches and ensures 14-bit linearity at full sample rates.
An on-chip track-and-hold (T/H) maintains superb
dynamic performance up to the Nyquist frequency. The
MAX1201 operates from a single +5V supply.
The fully differential inputs allow an input swing of
±VREF. A single-ended input is also possible using two
operational amplifiers. The reference is also differential
with the positive reference (RFPF) typically connected
to +4.096V and the negative reference (RFNF) tied to
analog ground. Additional sensing pins (RFPS, RFNS)
are provided to compensate for any resistive divider
action that may occur due to finite internal and external
resistances.
The power dissipation is typically only 269mW at +5V
and a sampling rate of 2.2Msps. The device employs a
CMOS compatible, 14-bit parallel, two’s complement out-
put data format. The MAX1201 is available in a 44-pin
MQFP package and is specified over the commercial
temperature (0°C to +70°C) and extended (-40°C to
+85°C) temperature ranges.
Features
o Monolithic 14-Bit, 2.2Msps ADC
o Signal-to-Noise Ratio of 83dB
o Spurious-Free Dynamic Range of 91dB
o Differential Nonlinearity Error: ±0.3LSB
o Integral Nonlinearity Error: ±1.2LSB
o Single +5V Analog Supply, +3V Digital Supply
o Low Power Dissipation: 269mW
o On-Demand Self-Calibration
o Three-State, Two’s Complement Output Data
PART
MAX1201CMH
MAX1201EMH
Ordering Information
TEMP. RANGE
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
44 MQFP
44 MQFP
Pin Configuration
xDSL
Instrumentation
Medical Imaging
Scanners
IR Imaging
Spectrum Analysis
Applications
TOP VIEW
ST_CAL
AGND
AVDD
AGND
AGND
AVDD
DOR
D13
D12
D11
D10
1
2
3
4
5
6
7
8
9
10
11
MAX1201
33 OE
32 DAV
31 CLK
30 DVDD
29 DGND
28 DGND
27 DVDD
26 TEST1
25 TEST2
24 TEST3
23 D0
MQFP
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
1 page  
+5V Single-Supply, 2.2Msps, 14-Bit
Self-Calibrating ADC
__________________________________________Typical Operating Characteristics
(AVDD = +5V, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, fCLK = 4.5056MHz, differential input, VCM = +2.048V, cal-
ibrated, TA = +25°C, unless otherwise noted.)
SINGLE-TONE SPURIOUS-FREE DYNAMIC
RANGE vs. INPUT AMPLITUDE (fIN = 100.1kHz)
110
100
90 dBFS
80
70 dBc
60
50
40
30
-70
-60 -50 -40 -30 -20 -10
INPUT AMPLITUDE (dBFS)
0
SIGNAL-TO-NOISE PLUS DISTORTION
vs. INPUT FREQUENCY
84
86 AIN = -0.5dBFS
82
80
78
76
74
72 AIN = -6dBFS
70
68 AIN = -20dBFS
66
64
62
60
1k
10k 100k
1M
INPUT FREQUENCY (Hz)
-70
-72
-74
-76
-78
-80
-82
-84
-86
-88
-90
1k
TOTAL HARMONIC DISTORTION
vs. INPUT FREQUENCY
AIN = -20dBFS
AIN = -6dBFS
AIN = -0.5dBFS
10k 100k
INPUT FREQUENCY (Hz)
1M
90
88
86
84
82
80
78
76
74
72
70
68
66
64
62
60
1k
SIGNAL-TO-NOISE-RATIO
vs. INPUT FREQUENCY
AIN = -0.5dBFS
AIN = -6dBFS
AIN = -20dBFS
10k 100k
INPUT FREQUENCY (Hz)
1M
SIGNAL-TO-NOISE-RATIO PLUS DISTORTION
vs. SAMPLE RATE (fIN = 100.1kHz)
90
88
86
84
82 AIN = -0.5dBFS
80
78
76
74
72
70
100k
1M
SAMPLE RATE (sps)
3M
0
-15
-30
-45
-60
-75
-90
-105
-120
-135
0
TYPICAL FFT, fIN = 100.1kHz,
2048 VALUE RECORD
200k 400k 600k 800k 1M 1.2M
FREQUENCY (Hz)
TYPICAL FFT, fIN = 1.0021MHz,
2048 VALUE RECORD
0
-15
-30
-45
-60
-75
-90
-105
-120
-135
0 200k 400k 600k 800k 1M 1.2M
FREQUENCY (Hz)
INTEGRAL NONLINEARITY vs.
TWO’S COMPLEMENT OUTPUT CODE
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-8192 -6144 -4096 -2048 0 2048 4096 6144 8192
TWO’S COMPLEMENT OUTPUT CODE
_______________________________________________________________________________________ 5
5 Page 
+5V Single-Supply, 2.2Msps, 14-Bit
Self-Calibrating ADC
Calibration Procedure
Since the MAX1201 is based on a pipelined architec-
ture, low-resolution quantizers (“coarse ADCs”) are
used to approximate the input signal. MDACs of the
same resolution are then used to reconstruct the input
signal, which is subtracted from the input and the
residue is amplified by the switched-capacitor gain
stage. This residue is then passed on to the next stage.
The accuracy of the MAX1201 is limited by the preci-
sion of the MDAC, which is strongly dependent on the
matching of the capacitors used. The mismatch
between the capacitors is determined and stored in an
on-chip memory, which is later used during the conver-
sion of the input signal.
During the calibration procedure, the clock must be
running continuously. ST_CAL (start of calibration) is
initiated by a positive pulse with a minimum width of
four clock cycles but no longer than about 17,400 clock
cycles (Figure 8).
The ST_CAL input may be asynchronous with the clock,
since it is retimed internally. With ST_CAL activated,
END_CAL goes low one or two clock cycles later and
remains low until the calibration is complete. During this
period, the reference voltages must be stable to less
than 0.01%; otherwise, the calibration will be invalid.
During calibration, the analog inputs INP and INN are
not used; however, better performance is achieved if
these inputs are static. Once END_CAL goes high (indi-
cating that the calibration procedure is complete), the
ADC is ready for conversion.
Once calibrated, the MAX1201 is insensitive to small
changes (±5%) in power supply, voltage, or tempera-
ture. Following calibration, if the temperature changes
more than ±20°C, the device should be recalibrated to
maintain optimum performance.
N
AIN
CLK
SAMPLE
CLOCK
tS
DAV
D0–D13
N+1
tCH tCL
N+2
N+3
N+4
N+5
tOD
N-3 N-2
N-1
N N+1
CLK
ST_CAL
END_CAL
MIN 4 tCLK
~17,400 CLK CYCLES
Figure 8. Timing for Start and End of Calibration
OE
D0–D13
DOR
Z
tAC
tREL
Z
Z = HIGH IMPEDANCE (THREE-STATED)
Figure 9. Timing for Bus Access and Bus Relinquish—
Controlled by Output Enable (OE)
Two’s Complement Output
The MAX1201 outputs data in two’s complement for-
mat. Table 1 shows how to convert the various full-
scale inputs into their two’s complement output codes.
Applications Information
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
error only and results directly from the ADC’s resolution
(N bits):
SNR(MAX) = (6.02 · N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is computed by taking
the ratio of the RMS signal to the RMS noise which
includes all spectral components minus the fundamen-
tal, the first nine harmonics, and the DC offset.
Figure 7. Main Timing Diagram
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MAX1201.PDF ] | |
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