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M74HC595
8-bit shift register with output latches (3-state)
SO16
TSSOP16
Features
• High speed: fMAX = 59 MHz (typ.) at VCC = 6 V
• Low power dissipation: ICC = 4 μA (max.)
at TA= 25 °C
• High noise immunity:
VNIH = VNIL = 28% VCC (min.)
• Symmetrical output impedance:
– |IOH| = IOL = 6 mA (min.) for QA to QH
– |IOH| = IOL = 4 mA (min.) for QH’
• Balanced propagation delays: tPLH ≅ tPHL
• Wide operating voltage range:
VCC (opr.) = 2 V to 6 V
• Pin and function compatible with 74 series 595
• ESD performance
– HBM: 2 kV
– MM: 200 V
– CDM: 1 kV
Datasheet - production data
Applications
• Automotive
• Industrial
• Computer
• Consumer
Description
The M74HC595 device is a high speed CMOS
8-bit shift register with output latches (3-state)
fabricated with silicon gate C2MOS technology.
This device contains an 8-bit serial in, parallel out
shift register that feeds an 8-bit D-type storage
register. The storage register has 8 3-state
outputs. Separate clocks are provided for both the
shift register and the storage register.
The shift register has direct overriding clear, serial
input, and serial output (standard) pins for
cascading. Both the shift register and storage
register use positive edge triggered clocks. If both
clocks are connected together, the shift register
state will always be one clock pulse ahead of the
storage register.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
Table 1. Device summary
Order code
Temperature range
Package
Packing
Marking
M74HC595RM13TR
M74HC595YRM13TR(1)
M74HC595TTR
M74HC595YTTR(1)
-55/+125 °C
-40/+125 °C
-55/+125 °C
-40/+125 °C
SO16
SO16 (automotive grade)
TSSOP16
TSSOP16 (automotive grade)
Tape and reel
74HC595
74HC595Y
HC595
HC595Y
1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC
Q001 and Q002 or equivalent.
January 2014
This is information on a product in full production.
DocID1989 Rev 6
1/22
www.st.com
M74HC595
Functional description
SI SCK
XX
XX
XX
L
H
X
XX
XX
1. X: don’t care.
Inputs
SCLR
X
X
L
H
H
H
X
X
Table 3. Truth table(1)
RCK
X
X
X
X
X
X
Outputs
G
H QA through QH outputs disable
L QA through QH outputs enable
X Shift register is cleared
X
First stage of S.R. becomes “L” other stages store the
data of previous stage, respectively
X
First stage of S.R. becomes “H” other stages store the
data of previous stage, respectively
X State of S.R. is not changed
X S.R. data is stored into storage register
X Storage register state is not changed
Figure 4. Input and output equivalent circuit
9&&
9&&
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287387
*1'
*1'
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DocID1989 Rev 6
5/22
22
M74HC595
Electrical characteristics
Table 8. Capacitive characteristics
Test condition
Value
Symbol
Parameter
VCC (V)
TA = 25 °C
Min. Typ. Max.
-40 to 85 °C
Min. Max.
-55 to 125 °C Unit
Min. Max.
CIN Input capacitance
CPD
Power dissipation
capacitance(1)
5 10 10 10
pF
184
1.
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from the operating
be obtained by the
current
following
equation: ICC(opr) = CPD x VCC x fIN + ICC.
Figure 6. Test circuit
Note:
Table 9. Propagation delay time configuration
Test Switch
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
Open
VCC
GND
CL = 50 pF/150 pF or equivalent (includes jig and probe capacitance)
R1 = 1 KΩ or equivalent
RT = ZOUT of pulse generator (typically 50 Ω).
DocID1989 Rev 6
11/22
22