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HD74HC595
8-bit Shift Register/Latch (with 3-state outputs)
Description
This device each contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift
register and the storage register. The shift register has a direct-overriding clear, serial input, and serial
output pins for cascading.
Both the shift register and storage register clocks are positive-edge triggered. If the user wishes to connect
both clocks together, the shift register state will always be one clock pulse ahead of the storage register.
Features
• High Speed Operation: tpd (RCK to Q) = 17 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads (QA to QH outputs)
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
RCK
X
X
X
SCK
X
X
X
SCLR
X
L
H
H
G
H
X
X
X
Function
QA to QH high impedance
Shift register cleared QH’ = L
Shift register clocked Qn = Qn – 1, QA = SER
Contents of shift register transferred to output latches
HD74HC595
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°C
Ta = –40 to
+85°C
Item
Maximum clock
frequency
Symbol
f max
VCC (V)
2.0
4.5
Min Typ Max Min
——5 —
— — 27 —
Max Unit Test Conditions
4 MHz
21
6.0 — — 31 — 24
Propagation delay tPLH
time
t PHL
2.0 — — 115 — 145 ns SCK to QH’
4.5 — 12 23 — 29
6.0 — — 20 — 25
tPLH 2.0 — — 150 — 190 ns RCK to Q
tPHL 4.5 — 17 30 — 38
6.0 — — 26 — 33
tPLH 2.0 — — 175 — 220 ns SCLR to QH’
4.5 — 20 35 — 44
6.0 — — 30 — 37
Output enable
time
t ZL
t ZH
2.0 — — 150 — 190 ns
4.5 — 13 30 — 38
6.0 — — 26 — 33
Output disable
time
t LZ
t HZ
2.0 — — 150 — 190 ns
4.5 — 15 30 — 38
6.0 — — 26 — 33
Setup time
tsu 2.0 100 — — 125 — ns SER to SCK
4.5 20 1 — 25 —
6.0 17 — — 21 —
2.0 200 — — 250 — ns SCK to RCK
4.5 40 8 — 50 —
6.0 34 — — 43 —
Pulse width tw 2.0 80 — — 100 — ns
4.5 16 8 — 20 —
6.0 14 — — 17 —
Removal time
t rem
2.0 100 — — 125 — ns
4.5 20 — — 25 —
6.0 17 — — 21 —
5