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PDF MCP602 Data sheet ( Hoja de datos )
| Número de pieza | MCP602 | |
| Descripción | 2.7V to 5.5V Single Supply CMOS Op Amps | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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MCP601/602/603/604
2.7V to 5.5V Single Supply CMOS Op Amps
FEATURES
• Specifications rated from 2.7V to 5.5V supplies
• Rail-to-rail swing at output
• Common-mode input swing below ground
• 2.8MHz GBWP
• Unity gain stable
• Low power IDD = 325µA max
• Chip Select capability with MCP603
• Industrial temperature range (-40°C to 85°C)
• Available in single, dual and quad
APPLICATIONS
• Portable Equipment
• A/D Converter Driver
• Photodiode Pre-amps
• Analog Filters
• Data Acquisition
• Notebooks and PDAs
• Sensor Interface
ates with a single supply voltage that can be as low as
2.7V, while drawing less than 325µA of quiescent cur-
rent. In addition, the common-mode input voltage
range goes 0.3V below ground, making these amplifi-
ers ideal for single supply operation.
These devices are appropriate for low-power battery
operated circuits due to the low quiescent current, for
A/D Converter driver amplifiers because of their wide
bandwidth, or for anti-aliasing filters by virtue of their
low input bias current.
The MCP601, MCP602 and MCP603 are available in
standard 8-lead PDIP, SOIC and TSSOP packages.
The MCP601 is also available in the SOT23-5 pack-
age. The quad MCP604 is offered in 14-lead PDIP,
SOIC and TSSOP packages. PDIP and SOIC pack-
ages are fully specified from -40°C to +85°C with power
supplies from 2.7V to 5.5V.
TYPICAL APPLICATION
AVAILABLE TOOLS
• Spice Macromodels (at www.microchip.com)
• FilterLab™ Software (at www.microchip.com)
2000 Microchip Technology Inc.
DESCRIPTION
The Microchip Technology Inc. MCP601/602/603/604
family of low power operational amplifiers are offered in
single (MCP601), single with a Chip Select pin feature
(MCP603), dual (MCP602) and quad (MCP604) config-
urations. These operational amplifiers (op amps) utilize
an advanced CMOS technology, which provides low
bias current, high speed operation, high open-loop gain
and rail-to-rail output swing. This product offering oper-
VIN
Low Input Bias
Current Over
Temperature
VDD
-IN
MCP60X
+IN
VREF
VSS
OUT
VOUT
Rail-to-Rail
Output Swing
2nd Order Low Pass Filter
PACKAGES
MCP601
PDIP, SOIC, TSSOP
MCP601
SOT23-5
MCP603
PDIP, SOIC, TSSOP
MCP602
PDIP, SOIC, TSSOP
MCP604
PDIP, SOIC, TSSOP
NC 1
-IN 2
+IN 3
VSS 4
-
+
8 NC
7 VDD
6 OUT
5 NC
OUT 1
VSS 2
+IN 3
+-
5 VDD
4 -IN
NC 1
-IN 2
+IN 3
VSS 4
-
+
8 CS OUTA 1
7 VDD -INA 2
6 OUT +INA 3
5 NC
VSS 4
-
A
+
+B-
8 VDD OUTA 1
7 OUTB -INA 2
6 -INB +INA 3
5 +INB VDD 4
+INB 5
-INB 6
OUTB 7
14 OUTD
-A+ +D- 13 -IND
12 +IND
11 VSS
10 +INC
-B+ +C- 9 -INC
8 OUTC
2000 Microchip Technology Inc.
DS21314D-page 1
1 page  
MCP601/602/603/604
Note: Unless otherwise indicated, VDD = +2.7V to +5.5V, TA = 25°C, VCM = VDD/2, RL = 25kΩ to VDD/2 and VOUT ~ VDD/2
40
35
VDD = 5.5V
RL = 100kΩ
Sample Size = 203 op amp
30
25
20
15
10
5
0
Offset Voltage (mV)
FIGURE 2-7: Offset Voltage vs.
Occurrences with VDD = 5.5V
Number
of
60
VDD = 5.5V
50
RL = 100kΩ
Sample Size = 203
Temperature Range = -40°C to +85°C
40
30
20
10
0
012345678
Change in Offset Voltage with Temperature (µV/°C)
FIGURE 2-10: Offset Voltage Drift vs. Number of
Occurrences with VDD = 5.5V
40
VDD = 2.7V
35 RL = 100kΩ
Sample Size = 203 op amp
30
25
20
15
10
5
0
Offset Voltage (mV)
FIGURE 2-8: Offset Voltage vs.
Occurrences with VDD = 2.7V.
Number
of
60
VDD = 2.7V
50 RL = 100kΩ
Sample Size = 203
Temperature Range = -40°C to +85°C
40
30
20
10
0
0 12345678
Change in Offset Voltage with Temperature (µV/°C)
FIGURE 2-11: Offset Voltage Drift vs. Number of
Occurrences with VDD = 2.7V
500
400
300
200
100
0
-100
-200
-300
-400
-500
-40
VDD = 2.7V
VDD = 5.5V
-20 0 20 40
Temperature (°C)
RL = 100kΩ
60 80
FIGURE 2-9: Normalized Offset Voltage vs. Temper-
ature with VDD = 2.7V
100
CMRR
VDD = 2.7V
95 VCM = -0.3V to 1.5V
PSRR,
VDD = 2.7V to 5.5V
90
CMRR
VDD = 5.5V
85 VCM = -0.3V to 4.3V
80
75
-40 -20
0
20 40 60 80
Temperature (° C)
FIGURE 2-12: Common-Mode Rejection Ratio,
Power Supply Rejection Ratio vs. Temperature
2000 Microchip Technology Inc.
DS21314D-page 5
5 Page 
The maximum operating common-mode voltage that
can be applied to the inputs is VSS - 0.3V to VDD - 1.2V.
In contrast, the absolute maximum input voltage is VSS
- 0.3V and VDD + 0.3V. Voltages on the input that
exceed this absolute maximum rating can cause exces-
sive current to flow in or out of the input pins. Current
beyond ±2mA can cause possible reliability problems.
Applications that exceed this rating must be externally
limited with an input resistor as shown in Figure 3-3.
MCP60X
RIN
RIN = (Maximum expected voltage - VDD) / 2mA
or
(VSS - Minimum expected voltage)/ 2mA.
FIGURE 3-3: If the inputs of the amplifier exceed the
Absolute Maximum Specifications, an input resistor,
RIN , should be used to limit the current flow into that
pin.
3.3 Capacitive Load and Stability
Driving capacitive loads can cause stability problems
with many of the higher speed amplifiers.
For any closed loop amplifier circuit, a good rule of
thumb is to design for a phase margin that is no less
than 45°. This is a conservative theoretical value, how-
ever, if the phase margin is lower, layout parasitics can
degrade the phase margin further causing a truly
unstable circuit. A system phase shift of 45° will have
an overshoot in its step response of approximately
25%.
A buffer configuration with a capacitive load is the most
difficult configuration for an amplifier to maintain stabil-
ity. The Phase versus Capacitive Load of the MCP60X
amplifier is shown in Figure 3-4. In this figure, it can be
seen that the amplifier has a phase margin above 40°,
while driving capacitance loads up to 100pF.
MCP601/602/603/604
4
3.5 Gain-Bandwidth
3
2.5
2 Phase
1.5 Margin
1
0.5
0
1100
110000 110E003 11000E030
Capacitance (pF)
80
VDD=5.0V,
RL=100 kΩ
70
60
50
40
30
20
10
0
1100000E030 10010E0600
FIGURE 3-4: Gain Bandwidth, Phase Margin vs.
Capacitive Load
VDD
MCP60X
VIN
RISO
VOUT
CL
FIGURE 3-5: Amplifier circuits that can be used
when driving heavy capacitive loads.
If the amplifier is required to drive larger capacitive
loads, the circuit shown in Figure 3-5 can be used. A
small series resistor (RISO) at the output of the amplifier
improves the phase margin when driving large capaci-
tive loads. This resistor decouples the capacitive load
from the amplifier by introducing a zero in the transfer
function.
This zero adjusts the phase margin by approximately:
∆θm = tan-1 (2π GBWP x RISO x CL)
where:
∆θm is the improvement in phase margin,
GBWP is the gain bandwidth product of the
amplifier,
RISO is the capacitive decoupling resistor, and
CL is the load capacitance
2000 Microchip Technology Inc.
DS21314D-page 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MCP602.PDF ] | |
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