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PDF MCP3002 Data sheet ( Hoja de datos )
| Número de pieza | MCP3002 | |
| Descripción | 2.7V Dual Channel 10-Bit A/D Converter | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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MCP3002
2.7V Dual Channel 10-Bit A/D Converter
with SPI™ Serial Interface
Features
• 10-bit resolution
• ±1 LSB max DNL
• ±1 LSB max INL
• Analog inputs programmable as single-ended or
pseudo-differential pairs
• On-chip sample and hold
• SPI™ serial interface (modes 0,0 and 1,1)
• Single supply operation: 2.7V - 5.5V
• 200 ksps max sampling rate at VDD = 5V
• 75 ksps max sampling rate at VDD = 2.7V
• Low power CMOS technology:
- 5 nA typical standby current, 2 µA max
- 550 µA max. active current at 5V
• Industrial temp range: -40°C to +85°C
• 8-pin MSOP, PDIP, SOIC and TSSOP packages
Applications
• Sensor Interface
• Process Control
• Data Acquisition
• Battery Operated Systems
Description
The Microchip Technology Inc. MCP3002 is a succes-
sive approximation 10-bit Analog-to-Digital (A/D) Con-
verter with on-board sample and hold circuitry. The
MCP3002 is programmable to provide a single pseudo-
differential input pair or dual single-ended inputs. Differ-
ential Nonlinearity (DNL) and Integral Nonlinearity
(INL) are both specified at ±1 LSB. Communication
with the device is done using a simple serial interface
compatible with the SPI protocol. The device is capable
of conversion rates of up to 200 ksps at 5V and 75 ksps
at 2.7V. The MCP3002 device operates over a broad
voltage range (2.7V - 5.5V). Low current design permits
operation with a typical standby current of 5 nA and a
typical active current of 375 µA. The MCP3002 is
offered in 8-pin MSOP, PDIP, TSSOP and 150 mil
SOIC packages.
Package Types
MSOP, PDIP, SOIC, TSSOP
CS/SHDN
CH0
CH1
VSS
1
2
3
4
8
7
6
5
VDD/VREF
CLK
DOUT
DIN
Functional Block Diagram
VDD VSS
CH0
CH1
Input
Channel
Mux
Sample
and
Hold
DAC
Comparator
10-Bit SAR
Control Logic
Shift
Register
CS/SHDN DIN CLK
DOUT
© 2007 Microchip Technology Inc.
DS21294C-page 1
1 page  
MCP3002
2.0 TYPICAL PERFORMANCE CHARACTERISTICS
Note:
The graphs provided following this note are a statistical summary based on a limited number of samples
and are provided for informational purposes only. The performance characteristics listed herein are not
tested or guaranteed. In some graphs, the data presented may be outside the specified operating range
(e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200 ksps, fCLK = 16* fSAMPLE,TA = 25°C
0.6
0.4
0.2 Positive INL
0.0
-0.2 Negative INL
-0.4
-0.6
0 25 50 75 100 125 150 175 200 225 250
Sample Rate (ksps)
FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample
Rate.
1.0
0.8 VDD = 5V
0.6 fSAMPLE = 200 ksps
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
128 256 384 512 640 768 896 1024
Digital Code
FIGURE 2-2: Integral Nonlinearity (INL) vs. Code.
0.5
0.4
0.3
0.2 Positive INL
0.1
0.0
-0.1
-0.2 Negative INL
-0.3
-0.4
-0.5
-50 -25 0 25 50 75 100
Temperature (°C)
FIGURE 2-3: Integral Nonlinearity (INL) vs.
Temperature.
0.6
VDD = 2.7V
0.4
0.2 Positive INL
0.0
-0.2
Negative INL
-0.4
-0.6
0
25 50
75
Sample Rate (ksps)
100
FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample
Rate (VDD = 2.7V).
1.0
0.8 VDD = 2.7V
0.6 fSAMPLE = 75 ksps
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
128 256 384 512 640 768 896 1024
Digital Code
FIGURE 2-5: Integral Nonlinearity (INL) vs. Code
(VDD = 2.7V).
0.5
0.4 VDD = 2.7V
0.3 fSAMPLE = 75 ksps
0.2 Positive INL
0.1
0.0
-0.1
-0.2
-0.3 Negative INL
-0.4
-0.5
-50 -25 0 25 50 75 100
Temperature (°C)
FIGURE 2-6: Integral Nonlinearity (INL) vs.
Temperature (VDD = 2.7V).
© 2007 Microchip Technology Inc.
DS21294C-page 5
5 Page 
3.0 PIN DESCRIPTIONS
3.1 CH0/CH1
Analog inputs for channels 0 and 1 respectively. These
channels can programmed to be used as two indepen-
dent channels in single ended-mode or as a single
pseudo-differential input where one channel is IN+ and
one channel is IN-. See Section 5.0 for information on
programming the channel configuration.
3.2 Chip Select/Shutdown (CS/SHDN)
The CS/SHDN pin is used to initiate communication
with the device when pulled low and will end a conver-
sion and put the device in low power standby when
pulled high. The CS/SHDN pin must be pulled high
between conversions.
3.3 Serial Clock (CLK)
The SPI clock pin is used to initiate a conversion and to
clock out each bit of the conversion as it takes place.
See Section 6.2 for constraints on clock speed.
3.4 Serial Data Input (DIN)
The SPI port serial data input pin is used to clock in
input channel configuration data.
3.5 Serial Data Output (DOUT)
The SPI serial data output pin is used to shift out the
results of the A/D conversion. Data will always change
on the falling edge of each clock as the conversion
takes place.
4.0 DEVICE OPERATION
The MCP3002 A/D converter employs a conventional
SAR architecture. With this architecture, a sample is
acquired on an internal sample/hold capacitor for
1.5 clock cycles starting on the second rising edge of
the serial clock after the start bit has been received.
Following this sample time, the input switch of the con-
verter opens and the device uses the collected charge
on the internal sample and hold capacitor to produce a
serial 10-bit digital output code. Conversion rates of
200 ksps are possible on the MCP3002. See
Section 6.2 for information on minimum clock rates.
Communication with the device is done using a 3-wire
SPI compatible interface.
4.1 Analog Inputs
The MCP3002 device offers the choice of using the ana-
log input channels configured as two single-ended
inputs that are referenced to VSS or a single pseudo-dif-
ferential input. The configuration setup is done as part of
the serial command before each conversion begins.
When used in the psuedo-differential mode, CH0 and
CH1 are programmed as the IN+ and IN- inputs as part
© 2007 Microchip Technology Inc.
MCP3002
of the command string transmitted to the device. The
IN+ input can range from IN- to the reference voltage,
VDD. The IN- input is limited to ±100 mV from the VSS
rail. The IN- input can be used to cancel small signal
common-mode noise which is present on both the IN+
and IN- inputs.
For the A/D converter to meet specification, the charge
holding capacitor (CSAMPLE) must be given enough time
to acquire a 10-bit accurate voltage level during the
1.5 clock cycle sampling period. The analog input
model is shown in Figure 4-1.
In this diagram, it is shown that the source impedance
(RS) adds to the internal sampling switch (RSS) imped-
ance, directly affecting the time that is required to
charge the capacitor, CSAMPLE. Consequently, larger
source impedances increase the offset, gain, and inte-
gral linearity errors of the conversion.
Ideally, the impedance of the signal source should be
near zero. This is achievable with an operational ampli-
fier such as the MCP601 which has a closed loop out-
put impedance of tens of ohms. The adverse affects of
higher source impedances are shown in Figure 4-2.
When operating in the pseudo-differential mode, if the
voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. If the voltage at IN+ is equal
to or greater than {[VDD + (IN-)] - 1 LSB}, then the out-
put code will be 3FFh. If the voltage level at IN- is more
than 1 LSB below VSS, then the voltage level at the IN+
input will have to go below VSS to see the 000h output
code. Conversely, if IN- is more than 1 LSB above VSS,
then the 3FFh code will not be seen unless the IN+
input level goes above VDD level. If the voltage at IN+
is equal to or greater than {[VDD + (IN-)] - 1 LSB}, then
the output code will be 3FFh.
4.2 Digital Output Code
The digital output code produced by an A/D Converter
is a function of the input signal and the reference volt-
age. For the MCP3002, VDD is used as the reference
voltage.
LSB Size = V-----R---E----F-
1024
As the VDD level is reduced, the LSB size is reduced
accordingly. The theoretical digital output code pro-
duced by the A/D Converter is shown below.
Digital Output Code = -1---0---2----4---*---V----I--N--
VDD
where:
VIN = analog input voltage
VDD = supply voltage
DS21294C-page 11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet MCP3002.PDF ] | |
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