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PDF LMU18JC35 Data sheet ( Hoja de datos )
| Número de pieza | LMU18JC35 | |
| Descripción | 16 x 16-bit Parallel Multiplier | |
| Fabricantes | LOGIC Devices Incorporated | |
| Logotipo |  |
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DEVICES INCORPORATED
DEVICES INCORPORATED
LMU18
LMU1816 x 16-bit Parallel Multiplier
16 x 16-bit Parallel Multiplier
FEATURES
DESCRIPTION
u 35 ns Worst-Case Multiply Time
u Low Power CMOS Technology
u Full 32-bit Output Port —
No Multiplexing Required
u Two’s Complement, Unsigned, or
Mixed Operands
u Three-State Outputs
u 84-pin PLCC, J-Lead
The LMU18 is a high-speed, low
power 16-bit parallel multiplier.
The LMU18 is an 84-pin device
which provides simultaneous access
to all outputs.
The LMU18 produces the 32-bit
product of two 16-bit numbers.
Data present at the A inputs, along
with the TCA control bit, is loaded
into the A register on the rising edge
of CLK. B data and the TCB control
bit are similarly loaded. Loading of
the A and B registers is controlled
LMU18 BLOCK DIAGRAM
CLK
ENA
ENB
TCA
A 15-0
16
A REGISTER
TCB B15-0
16
B REGISTER
RND
by the ENA and ENB controls. When
HIGH, these controls prevent appli-
cation of the clock to the respective
register. The TCA and TCB controls
specify the operands as two’s com-
plement when HIGH, or unsigned
magnitude when LOW.
RND is loaded on the rising edge of CLK,
providing either ENA or ENB are LOW.
RND, when HIGH, adds ‘1’ to the
most significant bit position of the
least significant half of the product.
Subsequent truncation of the 16 least
significant bits produces a result
correctly rounded to 16-bit precision.
At the output, the Right Shift control (RS)
selects either of two output formats. RS
LOW produces a 31-bit product with a
copy of the sign bit inserted in the MSB
postion of the least significant half. RS
HIGH gives a full 32-bit product. Two
16-bit output registers are provided to
hold the most and least significant
halves of the result (MSP and LSP) as
defined by RS. These registers are loaded
on the rising edge of CLK, subject to the
ENR control. When ENR is HIGH, clock-
ing of the result registers is prevented.
RS
FT
ENR
MSPSEL
32
FORMAT ADJUST
16 16
RESULT
REGISTER
OEM
16
OEL
16
For asynchronous output these registers
may be made transparent by setting the
feed through control (FT) HIGH and
ENR LOW.
The two halves of the product may be
routed to a single 16-bit three-state
output port (MSP) via a multiplexer.
MSPSEL LOW causes the MSP outputs to
be driven by the most significant half of
the result. MSPSEL HIGH routes the
least significant half of the result to the
MSP pins. The MSB of the result is avail-
able in both true and complemented
form to aid implementation of higher
precision multipliers.
R 31
R 31-16
R 15-0
Multipliers
1 08/16/2000–LDS.18-O
1 page  
DEVICES INCORPORATED
LMU18
16 x 16-bit Parallel Multiplier
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values beyond
those indicated in the Operating Condi-
tions table is not implied. Exposure to
maximum rating conditions for ex-
tended periods may affect reliability.
2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
cumulations of static charge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. Thisdeviceprovideshardclampingof
transient undershoot and overshoot. In-
put levels below ground or above VCC
will be clamped beginning at –0.6 V and
VCC + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of –0.5 V to +7.0 V. Device opera-
tion will not be adversely affected, how-
ever, input current levels will be well in
excess of 100 mA.
4. Actual test conditions may vary from
those designated but operation is guar-
anteed as specified.
5. Supply current for a given applica-
tion can be accurately approximated by:
where
NCV2 F
4
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of IOH and IOL respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
a. A 0.1 µF ceramic capacitor should be
installed between VCC and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device VCC
and the tester common, and device
ground and tester common.
b. Ground and VCC supply planes
must be brought directly to the DUT
socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing volt-
age, VTH, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
S1
DUT
CL
IOL
VTH
IOH
FIGURE B. THRESHOLD LEVELS
tENA
tDIS
OE 1.5 V
1.5 V
Z0
1.5 V
VOL* 0.2 V
3.5V Vth
0Z
Z1
1.5 V
VOH* 0.2 V
1Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
Multipliers
5 08/16/2000–LDS.18-O
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